Cirrus Logic EP93 Series User Manual page 19

EP93xx User's Guide
Table 8-2. bpp Memory Organization............................................................................................................8-5
Table 8-3. 4 bpp Memory Organization.........................................................................................................8-5
Table 8-4. 8 bpp Memory Organization.........................................................................................................8-6
Table 8-5. 16 bpp Memory Organization.......................................................................................................8-6
Table 8-6. 24 bpp Packed Memory Organization (4 pixel/ 3 words) .............................................................8-7
Table 8-7. 24 bpp Unpacked Memory Organization (1 pixel/ 1 word) ...........................................................8-7
Table 8-8. Transfer Example 1......................................................................................................................8-8
Table 8-9. Transfer Example 2......................................................................................................................8-9
Table 8-10. Transfer Example 3....................................................................................................................8-9
Table 8-11. Transfer Example 4....................................................................................................................8-9
Table 8-12. Transfer Example 5....................................................................................................................8-9
Table 8-13. 4 BPP Memory Layout for Source Image.................................................................................8-10
Table 8-14. 4 BPP Memory Layout for Destination Image ..........................................................................8-10
Table 8-15. 8 BPP Memory Layout for Source Image.................................................................................8-11
Table 8-16. 8 BPP Memory Layout for Destination Image ..........................................................................8-11
Table 8-17. 16 BPP Memory Layout for Source Image...............................................................................8-11
Table 8-18. 16 BPP Memory Layout for Destination Image ........................................................................8-12
Table 8-19. 24 BPP Memory Layout for Source Image...............................................................................8-12
Table 8-20. 24 BPP Memory Layout for Destination Image .......................................................................8-13
Table 8-21. Words Needed for Six 24-Bit Pixels .........................................................................................8-19
Table 8-22. Graphics Accelerator Registers ...............................................................................................8-22
Table 8-23. Pixel Mode Encoding ...............................................................................................................8-30
Table 9-1. FIFO RAM Address Map..............................................................................................................9-3
Table 9-2. RXCtl.MA and RXCtl.IAHA[0] Relationships ..............................................................................9-10
Table 9-3. Ethernet Register List.................................................................................................................9-40
Table 9-4. Individual Accept, RxFlow Control Enable and Pause Accept Bits ............................................9-42
Table 9-5. Address Filter Pointer.................................................................................................................9-52
Table 10-1. Data Transfer Size .................................................................................................................10-18
Table 10-2. M2P DMA Bus Arbitration ......................................................................................................10-19
Table 10-3. DMA Memory Map .................................................................................................................10-20
Table 10-4. Internal M2P/P2M Channel Register Map..............................................................................10-21
Table 10-5. PPALLOC Register Bits Decode for a Transmit Channel ......................................................10-24
Table 10-6. PPALLOC Register Bits Decode for a Receive Channel .......................................................10-24
Table 10-7. PPALLOC Register Reset Values..........................................................................................10-24
Table 10-8. PPALLOC Register Reset Values..........................................................................................10-30
Table 10-9. BWC Decode Values .............................................................................................................10-33
Table 10-10. DMA Global Interrupt (DMAGlInt) Register ..........................................................................10-45
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