Cirrus Logic EP93 Series User Manual page 378

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
RXStsQBLen
9
31 30
15 14
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
RXStsQCurLen
31 30
15 14
Address:
Chip Reset:
Soft Reset:
9-76
29 28 27 26
13 12 11 10
0x8001_00A4 - Read/Write
0x0000_0000
Unchanged
Receive Status Queue Base Length. The Receive Status Queue Base Length
defines the actual number of bytes in the receive status queue. The length
should be set at initialization time and must define an integral number of
receive statuses.
RSVD:
RSQBL:
29 28 27 26
13 12 11 10
0x8001_00A6 - Read/Write. Note half word alignment.
0x0000_0000
Unchanged
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
RSQBL
Reserved. Unknown During Read.
Receive Status Queue Base Length.
25 24 23 22
RSVD
9 8 7 6
RSQCL
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1