Cirrus Logic EP93 Series User Manual page 376

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
RXDEnq
9
31 30
15 14
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
RXBCA
31 30
15 14
Address:
9-74
29 28 27 26
13 12 11 10
RSVD
0x8001_009C - Read/Write
0x0000_0000
Unchanged
Receive Descriptor Enqueue register. The Receive Descriptor Enqueue
register is used to define the number of valid entries in the descriptor queue.
The register operates as follows: only the Receive descriptor Increment field is
writable and any value written to this field is added to the existing Receive
Descriptor Value. Whenever complete descriptors are read by the MAC, the
Receive Descriptor Value is decremented by the number read. For example, if
the Receive Descriptor Value is 0x07 and the Host writes 03 to the Receive
Descriptor Increment, the new Value will be 0x0A. If the controller then reads
two descriptors, the Value will be 0x08.
RSVD:
RDV:
RDI:
29 28 27 26
13 12 11 10
0x8001_0088 - Read/Write
Copyright 2007 Cirrus Logic
25 24 23 22
RDV
9 8 7 6
Reserved. Unknown During Read.
Receive Descriptor Value.
Receive Descriptor Increment.
25 24 23 22
RBCA
9 8 7 6
RBCA
21 20 19 18
5 4 3 2
RDI
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1