Cirrus Logic EP93 Series User Manual page 701

TXBUSY:
TXFF:
RXFF:
TXFE:
RXFE:
AC97RISRx
31 30 29 28
15 14 13 12
Address:
AC97RISR1 - 0x8088_0010 - Read Only
AC97RISR2 - 0x8088_0030 - Read Only
AC97RISR3 - 0x8088_0050 - Read Only
AC97RISR4 - 0x8088_0070 - Read Only
Definition:
Raw Interrupt Status. The AC97ISR registers are the raw Interrupt status
registers for the controller FIFOs. All bits are cleared to zero on reset except
for the TCIS as the FIFO and shift register should both be empty. Any write to
this register clears the overrun error.
Bit Descriptions:
RSVD:
RIS:
TIS:
DS785UM1
TXBUSY is set when TEN = "1" AND there is data in the
FIFO, OR when data from this FIFO is being sent in the
current frame.
TXBUSY is cleared at the start of the next frame following
the assertion of the corresponding channel's TXFE flag
(the value of TEN is irrelevant).
Transmit FIFO full flag, active HIGH.
This bit is asserted HIGH if the transmit FIFO is full.
Receive FIFO full flag, active HIGH.
This bit is asserted HIGH if the receive FIFO is full.
Transmit FIFO empty flag, active HIGH.
This bit is asserted HIGH if the transmit FIFO is empty.
Receive FIFO empty flag, active HIGH.
This bit is asserted HIGH if the receive FIFO is empty.
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read.
RX Interrupt Status - This bit is set to "1" if the receive
FIFO becomes half full.
TX Interrupt Status - This bit is set to "1" if the transmit
FIFO becomes half empty.
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
AC'97 Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
RIS TIS RTIS TCIS
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