Table 4-1. Boot Configuration Options - Cirrus Logic EP93 Series User Manual

Arm 9 embedded processor family
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EECLK EEDAT BOOT1
0
1
0
1
1
1
1
1
1
1
1
1
Note: ASYNC boot mode is the preferred boot mode type for new designs.
DS785UM1

Table 4-1. Boot Configuration Options

BOOT0 ASDO CSn[7:6]
0
0
1
0
0
0
0
1
x
0
0
x
0
0
1
0
0
0
Copyright 2007 Cirrus Logic
Boot Configuration
External boot using Sync boot mode and SDCSn3.
The media type must be either SyncROM or
SyncFLASH. The selection of the bus width is
determined by latched CSn[7:6] value:
16-bit
0 0
16-bit
0 1
32-bit
1 0
32-bit
1 1
External boot using Async boot mode and CSn0. The
selection of the bus width is determined by latched
CSn[7:6] value:
8-bit
0 0
16-bit
0 1
32-bit
1 0
32-bit
1 1
xx
Internal boot from UART1.
xx
Internal SPI boot if HeaderID is found.
Internal boot using SYNC boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
0 0
16-bit
0 1
16-bit
1 0
32-bit
1 1
32-bit
See memory map in
Table 2-7 on page 2-16
boot mode.
Internal boot using ASYNC boot mode at the chip
select where the HeaderID exists. The selection of the
bus width is determined by latched CSn[7:6] value:
0 0
8-bit
0 1
16-bit
1 0
32-bit
1 1
32-bit
See memory map in
Table 2-7 on page 2-16
ASYNC boot mode.
Boot ROM
EP93xx User's Guide
for SYNC
for
4-5
4

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