Table 8-23. Pixel Mode Encoding - Cirrus Logic EP93 Series User Manual

Graphics Accelerator
EP93xx User's Guide
BLOCKCTRL
8
31 30
15 14
INTEOI BG REMAP
Address:
Default:
Mask:
Definition:
Bit Descriptions:
8-30
29 28 27 26
RSVD
13 12 11 10
D1 D0 M1
0x8004_0024 - Read/Write
0x0000_0000
0x001F_FFFF
Block Function Control Register
RSVD:
PACKD:
P:

Table 8-23. Pixel Mode Encoding

P2 P1
0 0
0 0
0 1
Copyright 2007 Cirrus Logic
25 24 23 22
9 8 7 6
M0 SYDIR SXDIR DYDIR
Reserved - Unknown during read
Packed Image Bit - Read/Write
This bit is normally '0' to indicate that the source and
destination images during a Block Copy function are the
same size.
When this bit is '1', the a block transfer image source is
stored in packed format. Packed format indicates that the
source image is not the same dimensions as the
destination image, and that source information transfers
are whole words with the possible exceptions of the
beginning and ending words. This allows images to be
packed into any square configuration of whole words,
including a serial stream.
Bits Per Pixel - Read/Write
The value of this field, as shown in
the pixel mode (depth) that is used for Graphics
Accelerator functions. The Raster Engine has a similar
pixel depth field, but it's value is independent from this P
value and may be either different or the same.
P0 Pixel Mode
0 not defined
1 4 bit per pixel
0 8 bits per pixel
21 20 19 18
PACKD P
5 4 3 2
DXDIR LINE FILL TRANS
Table 8-23, specifies
17 16
ERROR
1 0
INTEN EN
DS785UM1