Cirrus Logic CS5346 Manuals

Manuals and User Guides for Cirrus Logic CS5346. We have 1 Cirrus Logic CS5346 manual available for free PDF download: Manual

Cirrus Logic CS5346 Manual (38 pages)

103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux

Brand: Cirrus Logic | Category: Computer Hardware | Size: 0 MB

Table of Contents
2
Pin Descriptions - Cs5346
5
Pin Compatibility - Cs5345/Cs5346 Differences
7
Characteristics and Specifications
8
Recommended Operating Conditions
8
Absolute Maximum Ratings
8
Analog Characteristics
9
Analog Characteristics Cont
10
Digital Filter Characteristics
11
DC Electrical Characteristics
12
Digital Interface Characteristics
13
Switching Characteristics - Serial Audio Port
14
Figure 1.Master Mode Serial Audio Port Timing
15
Figure 2.Slave Mode Serial Audio Port Timing
15
Figure 3.Format 0, 24-Bit Data Left-Justified
15
Figure 4.Format 1, 24-Bit Data I²S
15
Switching Characteristics - Control Port - I²C Format
16
Figure 5.Control Port Timing - I²C Format
16
Switching Characteristics - Control Port - Spi Format
17
Figure 6.Control Port Timing - SPI Format
17
Typical Connection Diagram
18
Figure 7.Typical Connection Diagram
18
Figure 10.CS5346
18
Applications
19
Recommended Power-Up Sequence
19
System Clocking
19
Master Clock
19
Table 1. Speed Modes
19
Table 2. Common Clock Frequencies
19
Master Mode
20
Slave Mode
20
High-Pass Filter and DC Offset Calibration
20
Figure 8.Master Mode Clocking
20
Table 3. Slave Mode Serial Bit Clock Ratios
20
Analog Input Multiplexer, PGA, and MIC Gain
21
Input Connections
21
Analog Input Configuration for 1 VRMS Input Levels
21
Figure 9.Analog Input Architecture
21
Analog Input Configuration for 2 VRMS Input Levels
22
Figure 11.1
22
Figure 12.1
22
Figure 13.2
22
PGA Auxiliary Analog Output
23
Control Port Description and Timing
23
SPI Mode
23
I²C Mode
24
Figure 14.Control Port Timing in SPI Mode
24
Figure 15.Control Port Timing, I²C Write
24
Interrupts and Overflow
25
Figure 16.Control Port Timing, I²C Read
25
Reset
26
Synchronization of Multiple Devices
26
Grounding and Power Supply Decoupling
26
Register Quick Reference
27
Register Description
28
Chip ID - Register 01H
28
Power Control - Address 02H
28
Freeze (Bit 7)
28
Power-Down MIC (Bit 3)
28
Power-Down ADC (Bit 2)
28
Power-Down Device (Bit 0)
28
Table 4. Device Revision
28
Table 5. Freeze-Able Bits
28
ADC Control - Address 04H
29
Functional Mode (Bits 7:6)
29
Digital Interface Format (Bit 4)
29
Mute (Bit 2)
29
High-Pass Filter Freeze (Bit 1)
29
Master / Slave Mode (Bit 0)
29
Table 6. Functional Mode Selection
29
Table 7. Digital Interface Formats
29
MCLK Frequency - Address 05H
30
Master Clock Dividers (Bits 6:4)
30
Pgaout Control - Address 06H
30
Pgaout Source Select (Bit 6)
30
Channel B PGA Control - Address 07H
30
Channel B PGA Gain (Bits 5:0)
30
Table 8. MCLK Frequency
30
Table 9. Pgaout Source Selection
30
Channel a PGA Control - Address 08H
31
Channel a PGA Gain (Bits 5:0)
31
ADC Input Control - Address 09H
31
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
31
Table 10. Example Gain and Attenuation Settings
31
Analog Input Selection (Bits 2:0)
32
Active Level Control - Address 0Ch
32
Active High/ Low (Bit 0)
32
Status - Address 0Dh
32
Table 11. PGA Soft Cross or Zero Cross Mode Selection
32
Table 12. Analog Input Multiplexer Selection
32
Clock Error (Bit 3)
33
Overflow (Bit 1)
33
Underflow (Bit 0)
33
Status Mask - Address 0Eh
33
Status Mode MSB - Address 0Fh
33
Status Mode LSB - Address 10H
33
Parameter Definitions
34
Filter Plots
35
Figure 17.Single-Speed Stopband Rejection
35
Figure 18.Single-Speed Stopband Rejection
35
Figure 19.Single-Speed Transition Band (Detail)
35
Figure 20.Single-Speed Passband Ripple
35
Figure 21.Double-Speed Stopband Rejection
35
Figure 22.Double-Speed Stopband Rejection
35
Figure 23.Double-Speed Transition Band (Detail)
36
Figure 24.Double-Speed Passband Ripple
36
Figure 25.Quad-Speed Stopband Rejection
36
Figure 26.Quad-Speed Stopband Rejection
36
Figure 27.Quad-Speed Transition Band (Detail)
36
Figure 28.Quad-Speed Passband Ripple
36
Package Dimensions
37
Thermal Characteristics and Specifications
37
Ordering Information
38
Revision History
38

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