Registers; Table 27-6. Ide Interface Register Map - Cirrus Logic EP93 Series User Manual

IDE Interface
EP93xx User's Guide
For both PIO and MDMA modes, the actual throughput is limited by the ARM Core's ability to
service requests, not raw bandwidth. For UDMA, the throughput is dependent on the
bandwidth available to the DMA controller.

27.3 Registers

27
Register Descriptions
IDECtrl
31 30
15 14
Address:
Default:
Definition:
27-10
Address
0x800A_0000
0x800A_0004
0x800A_0008
0x800A_000C
0x800A_0010
0x800A_0014
0x800A_0018
0x800A_001C
0x800A_0020
0x800A_0024
0x800A_0028
0x800A_002C
0x800A_0030
0x800A_0034
29 28 27 26
13 12 11 10
RSVD IORDY
0x800A_0000 - Read/Write
0x0000_0063
IDE Control Register. This register is used for IDE PIO control operations.
IORDY, INTRQ, DMARQ, and DASPn reflect external pins. Their reset state
can vary depending on system implementation and system configuration.

Table 27-6. IDE Interface Register Map

Name
IDECtrl
IDECfg
IDEMDMAOp
IDEUDMAOp
IDEDataOut
IDEDataIn
IDEMDMADataOut
IDEMDMADataIn
IDEUDMADataOut
IDEUDMADataIn
IDEUDMASts
IDEUDMADebug
IDEUDMAWrBufSts
IDEUDMARdBufSts
25 24 23 22
RSVD
9 8 7 6
INTRQ DMARQ DASPn DIOWn
Copyright 2007 Cirrus Logic
Description
IDE Control Register
IDE Configuration Register
IDE MDMA Operation Register
IDE UDMA Operation Register
IDE PIO Data Output Register
IDE PIO Data Input Register
IDE MDMA Data Output Register
IDE MDMA Data Input Register
IDE UDMA Data Output Register
IDE UDMA Data Input Register
IDE UDMA Status Register
IDE UDMA Debug Register
IDE UDMA Write Buffer Status Register
IDE UDMA Read Buffer Status Register
21 20 19 18
5 4 3 2
DIORn DA
17 16
1 0
CS1n CS0n
DS785UM1