Cirrus Logic EP93 Series User Manual page 95

Move Lower Half Double Precision Float from MaverickCrunch to ARM
31:28 27:24
cond 1 1 1 0
Description:
Moves the lower half of a double precision floating point value stored in a
MaverickCrunch register into an ARM register.
Mnemonic:
CFMVRDL<cond> Rd, CRn
Bit Definitions:
Rd:
CRn:
Move Upper Half Double Precision Float from ARM to MaverickCrunch
31:28 27:24
cond 1 1 1 0
Description:
Moves the upper half of a double precision floating point value from an ARM
register into the upper half of a MaverickCrunch register.
Mnemonic:
CFMVDHR<cond> CRn, Rd
Bit Definitions:
CRn:
Rd:
Move Upper Half Double Precision Float from MaverickCrunch to ARM
31:28 27:24
cond 1 1 1 0
Description:
Moves the upper half of a double precision floating point value stored in a
MaverickCrunch register into an ARM register.
Mnemonic:
CFMVRDH<cond> Rd, CRn
Bit Definitions:
Rd:
CRn:
DS785UM1
23:22 21 20 19:16
0 0 0 1 CRn
Destination ARM register
Source register
23:22 21 20 19:16
0 0 0 0 CRn
Destination register
Source ARM register
23:22 21 20 19:16
0 0 0 1 CRn
Destination ARM register
Source register
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
15:12 11:8
Rd 0 1 0 0 0 0 0
15:12 11:8
Rd 0 1 0 0 0 0 1
15:12 11:8
Rd 0 1 0 0 0 0 1
EP93xx User's Guide
7:5 4 3:0
1 CRm
7:5 4 3:0
1 CRm
7:5 4 3:0
1 CRm
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