Table 10-9. Bwc Decode Values - Cirrus Logic EP93 Series User Manual

PW:
DS785UM1
Example: if BWC = 1010b (indicating 1024 bytes, see
Table 10-9, below), the DMA relinquishes control of the
bus on completion of the current burst transfer after BCR
values which are within 15 bytes of multiples of 1024.

Table 10-9. BWC Decode Values

BWC
0000 Full DMA transfer completes
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Peripheral Width. For external DMA transfers, these bits
are used to program the DMA to request byte/half-
word/word wide AHB transfers, depending on the width of
the external device. These bits are not used for software
triggered M2M transfers.
00 - Byte (8 bits)
01 - Half-word (16 bits)
10 - Word (32 bits)
11 - Not used
For word accesses the lower 2 bits of the
source/destination address are ignored.
For half-word accesses the lower bit of the
source/destination address is ignored.
Copyright 2007 Cirrus Logic
Bytes
16
16
16
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
DMA Controller
EP93xx User's Guide
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