Cirrus Logic EP93 Series User Manual page 222

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
VBlankStrtStop
7
31 30
RSVD
15 14
RSVD
Address: 0x8003_0228
Default: 0x0000_0000
Definition: Vertical BLANK signal Start/Stop register
Bit Descriptions:
7-40
29 28 27 26
13 12 11 10
RSVD:
STOP:
STRT:
Copyright 2007 Cirrus Logic
25 24 23 22
9 8 7 6
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VBLANKn signal becomes inactive (stops).
This is used to generate the BLANKn signal that is used
by external devices and indicates the end of the active
video portion for the Vertical frame. Please refer to video
signalling timing diagrams in
VBLANKn is an internal block signal. The NBLANK output
is a logical AND of NVBLANK and HBLANKn.
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VBLANKn signal becomes active (starts).
This is used to generate the BLANKn signal that is used
by external devices and indicates the start of the active
video portion for the Vertical frame. Please refer to video
signalling timing diagrams in
VBLANKn is an internal block signal. The NBLANK output
is a logical AND of NVBLANK and HBLANKn.
21 20 19 18
STOP
5 4 3 2
STRT
Figure 7-9 and Figure
Figure 7-9 and Figure
17 16
1 0
7-10.
7-10.
DS785UM1