Cirrus Logic EP93 Series User Manual page 142

System Controller
EP93xx User's Guide
5
5-16
DMA M2M/P CHx: These bits enable the clocks to the DMA controller
channels. Note that a channels-enable bit MUST be
asserted before any register within the DMA controller can
be read or written. At least one ARM instruction cycle must
occur between writing to this register to enable the DMA
Controller channel and actually accessing it. The number
of cycles will depend on the setting of HCLK and PCLK
division in the
power, ensure that all these bits are disabled (low) if the
DMA controller is not being used. On a system reset, the
register will be reset to zero.
USH_EN: This bit is used to gate the HCLK to the USB Host block in
order to save power. It is reset to zero, thus gating off the
HCLK. It can be set to one to turn on the HCLK to the USB
Host. This bit must be set before any register within the
USB Host can be accessed. At least one ARM instruction
cycle must occur between writing to this register bit and
actually accessing the USB Host. The number of cycles
will depend on the setting of HCLK and PCLK division in
the
This bit is also used to gate the 48 MHz and 12 MHz
clocks to the USB Host block in order to save power. It is
reset to zero, thus gating off the USB Host clocks. By
setting this to one, the USB Host clocks are enabled. At
least one ARM instruction cycle must occur between
writing to this register bit and actually accessing the USB
Host. The number of cycles will depend on the wake-up
time for PLL2. To find out if PLL2 has locked on to its
frequency, the PLL2_LOCK bit in the PwrSts register can
be read.
UARTBAUD: This bit controls the clock input to the UARTs. When
cleared, the UARTs are driven by the 14.7456 MHz clock
divided by 2 (7.3728 MHz). This gives a maximum baud-
rate of 230 Kbps. When set, the UARTs are driven by the
14.7456 MHz clock directly, giving an increased maximum
baud rate of 460 Kbps. This bit is 0 on reset.
FIR_EN: This bit is used to gate the FIRCLK to the IrDA block in
order to save power. It is reset to zero, thus gating off the
FIRCLK. Setting this bit to one will turn on the 48 MHz
clock to the IrDA.
Copyright 2007 Cirrus Logic
"ClkSet1" or
"ClkSet1" and "ClkSet2"
"ClkSet2" register. To save
register.s
DS785UM1