Cirrus Logic EP93 Series User Manual page 653

RTCMatch
31 30 29 28
15 14 13 12
Address:
0x8092_0004 - Read/Write
Default:
0x0000_0000
Definition:
RTC Match Register. Contain the 32 bit match value. When the RTCData
value equals the RTCMatch value the RTC will generate an interrupt if the
RTCCtrl.MIE bit is set to "1".
Bit Descriptions:
RTCMR:
RTCSts
31 30 29 28
15 14 13 12
Address:
0x8092_0008 - Read/Write
Default:
0x0000_0000
Definition:
RTC Interrupt Status and End Of Interrupt Register. Writing to this register
clears the asserted interrupt.
Bit Descriptions:
RSVD:
INTR:
DS785UM1
27 26 25 24
RTCMR
11 10 9 8
RTCMR
Match value.
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved, unknown during read.
Interrupt status,
1 - RTC interrupt is asserted
0 - no interrupt.
Copyright 2007 Cirrus Logic
Real Time Clock With Software Trim
23 22 21 20
7 6 5 4
23 22 21 20
7 6 5 4
EP93xx User's Guide
19 18 17 16
3 2 1 0
19 18 17 16
3 2 1 0
INTR
20-5
20