Cirrus Logic EP93 Series User Manual page 786

IDE Interface
EP93xx User's Guide
Bit Descriptions:
27
IDEUDMADataIn
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
IDEUDMASts
31 30
15 14
Address:
Default:
27-16
addressed and written by the DMA controller. A write by the host during UDMA
data-out operation will erroneously interfere with the UDMA state machine.
Any read will return zero.
IDEDD:
29 28 27 26
13 12 11 10
0x800A_0024 - Read Only (should be read by the DMA controller only)
0x0000_0000
In UDMA data-in operations, this register contains the data at the head of the
input buffer to be transferred by the DMA controller. The data is read from this
register by the DMA controller. This register should only be addressed and
read by the DMA controller. A read by the host during UDMA data-in operation
will erroneously interfere with the UDMA state machine. Any write is ignored.
IDEDD:
29 28 27 26
RSVD N4X
13 12 11 10
RSVD DSDD
0x800A_0028 - Read Only
0x0000_0000
IDE output data at the tail of the output buffer in UDMA
mode.
25 24 23 22
IDEDD
9 8 7 6
IDEDD
IDE input data at the head of the input buffer in UDMA
mode.
25 24 23 22
NDI NDO
9 8 7 6
DMARQ DDOE DM STOP
Copyright 2007 Cirrus Logic
21 20 19 18
5 4 3 2
21 20 19 18
RSVD SBUSY
5 4 3 2
HSHD DA
17 16
1 0
17 16
INTide DMAide
1 0
CS1n CS0n
DS785UM1