Cirrus Logic EP93 Series User Manual page 789

Bit Descriptions:
RSVD:
HPTR:
TPTR:
EMPTY:
HOM:
NFULL:
FULL:
CRC:
IDEUDMARdBufSts
31 30 29 28
15 14 13 12
RSVD
Address:
0x800A_0034 - Read Only
Default:
0000_0100
Definition:
Status register for UDMA read buffer.
Bit Descriptions:
RSVD:
HPTR:
TPTR:
EMPTY:
HOM:
NFULL:
FULL:
CRC:
DS785UM1
Reserved. Unknown during read, ignored during writes.
Head pointer in the write buffer.
Tail pointer in the write buffer.
Write buffer empty status.
Half or more entries in write buffer filled status.
Write buffer near full status.
Write buffer full status.
CRC result for data-out operation. Reset to 0x4ABA after
finishing UDMA operation.
27 26 25 24
CRC
11 10 9 8
FULL NFULL HOM EMPTY
Reserved. Unknown during read, ignored during writes.
Head pointer in the read buffer.
Tail pointer in the read buffer.
Read buffer empty status.
Half or more entries in read buffer filled status.
Read buffer near full status.
Read buffer full status.
CRC result for data-in operation. Reset back to 0x4ABA
after finishing UDMA operation.
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
TPTR
IDE Interface
EP93xx User's Guide
19 18 17 16
3 2 1 0
HPTR
27-19
27