Cirrus Logic EP93 Series User Manual page 158

System Controller
EP93xx User's Guide
5
KeyTchClkDiv
31 30
TSEN
15 14
KEN
Address:
Default:
Definition:
Bit Descriptions:
5-32
SDIV:
MENA:
ESEL:
PSEL:
PDIV:
MDIV:
29 28 27 26
13 12 11 10
0x8093_0090 - Read/Write, Software locked
0x0000_0000
Configures the Key Matrix, Touchscreen, and ADC clocks. Touchscreen clock
is a fixed divide-by-4 from the ADC clock. Touch Filter clock is a fixed divide-
by-2 from the ADC clock.
RSVD:
TSEN:
Copyright 2007 Cirrus Logic
SCLK divide select.
1 - SCLK = MCLK / 4,
0 - SCLK = MCLK / 2.
Enable master clock generation.
External clock source select.
0 - Use the external XTALI clock input as the clock source.
1 - Use one of the internal PLLs selected by PSEL as the
clock source.
PLL source select.
1 - Select PLL2 as the clock source.
0 - Select PLL1 as the clock source.
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
MCLK divider value. Forms a divide-by-N of the pre-divide
clock output. MCLK is the source clock divided by PDIV
divided by N.
25 24 23 22
RSVD
9 8 7 6
RSVD
Reserved. Unknown During Read.
Touchscreen and ADC clock enable
21 20 19 18
5 4 3 2
17 16
ADIV
1 0
KDIV
DS785UM1