Cirrus Logic EP93 Series User Manual page 64

ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User's Guide
2
Address
0x8082_003C
0x8082_0040
0x8082_0044
0x8082_0048
0x8082_004C
0x8082_0050
0x8082_0054
0x8082_0058
0x8082_005C
0x8082_0060
0x8082_0064
0x8082_0068
0x8082_006C
0x8083_xxxx
0x8083_2714
0x8084_xxxx
0x8084_0000
0x8084_0004
0x8084_0008
0x8084_000C
0x8084_0010
0x8084_0014
0x8084_0018
0x8084_001C
0x8084_0020
0x8084_0024
0x8084_0028 - 0x8084_002C
0x8084_0030
0x8084_0034
0x8084_0038
0x8084_003C
0x8084_0040
0x8084_0044
0x8084_0048
0x8084_004C
0x8084_0050
0x8084_0054
0x8084_0058
2-26
Table 2-8. Internal Register Map (Continued)
Register Name
I2STX2En
I2SRX0Lft
I2SRX0Rt
I2SRX1Lft
I2SRX1Rt
I2SRX2Lft
I2SRX2Rt
I2SRXLinCtrlData
I2SRXCtrl
I2SRXWrdLen
I2SRX0En
I2SRX1En
I2SRX2En
SECURITY
ExtensionID
Contact Cirrus Logic for details regarding implementation of device Security measures.
GPIO
PADR
PBDR
PCDR
PDDR
PADDR
PBDDR
PCDDR
PDDDR
PEDR
PEDDR
PFDR
PFDDR
PGDR
PGDDR
PHDR
PHDDR
GPIOFIntType1
GPIOFIntType2
GPIOFEOI
GPIOFIntEn
Copyright 2007 Cirrus Logic
Register Description
TX2 Channel Enable
Left Receive data Register for channel 0
Right Receive data Register for channel 0
Left Receive data Register for channel 1
Right Receive data Register for channel 1
Left Receive data Register for channel 2
Right Receive data Register for channel 2
Receive Line Control Register
Receive Control Register
Receive Word Length
RX0 Channel Enable
RX1 Channel Enable
RX2 Channel Enable
Security Registers
Contains the Part ID for EP93XX devices
GPIO Control Registers
GPIO Port A Data Register
GPIO Port B Data Register
GPIO Port C Data Register
GPIO Port D Data Register
GPIO Port A Data Direction Register
GPIO Port B Data Direction Register
GPIO Port C Data Direction Register
GPIO Port D Data Direction Register
GPIO Port E Data Register
GPIO Port E Data Direction Register
Reserved
GPIO Port F Data Register
GPIO Port F Data Direction Register
GPIO Port G Data Register
GPIO Port G Data Direction Register
GPIO Port H Data Register
GPIO Port H Data Direction Register
Reserved
Register controlling type, level or edge, of interrupt generated by
the pins of Port F
Register controlling polarity, high/low or rising/falling, of interrupt
generated by Port F
GPIO Port F End Of Interrupt Register
Interrupt Enable for Port F
SW
Lock
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
DS785UM1