Table 7-3. Output Pixel Transfer Modes - Cirrus Logic EP93 Series User Manual

Shift Color Output
P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) P(4) P(3) P(2) P(1) P(0)
Mode Mode Mode
single pixel
0x0
per clock up
0x0 0x4 R(1) R(0) G(1)
to 24 bits
0x8
wide
single 16-bit
0x0 0x5 565 pixel per R(3) R(2) G(5)
clock
single 16-bit
0x0 0x6 555 pixel per R(3) R(2) G(3)
clock
single 24-bit
0x0
pixel mapped
0x1 0x4 X X X
to 18 bits
0x8
each clk
single 16-bit
565 pixel
0x1 0x5 mapped to X X X
18 bits each
clk
single 16-bit
555 pixel
0x1 0x6 mapped to X X X
18 bits each
clk
P1(20) P1(12) P1(4)
0x2 progressive R1(4) G1(4) B1(4)
scan * * *
0x0
Lower Lower Lower
0x8 2 pixels per
P(20) P(12) P(4)
shift clock
R(4) G(4) B(4)
* * *
dual scan
P3(14) P3(6) P2(14)
progressive
0x3 G3(6) B3(6) B2(6)
scan
* * *
0x0
Lower Lower Upper
0x8 4 pixels per
P1(14) P1(6) P1(14)
shift clock
G1(6) B1(6) G1(6)
dual scan
* * *
P7(23) P6(23) P5(23)
progressive
0x4 R7 R6 R5
scan
* * *
0x0
Lower Upper Lower
0x8 8 pixels per
P3(23) P3(23) P2(23)
shift clock
R3 R3 R2
dual scan
* * *
X X X
0x0
2 2/3 pixels
0x5 0x8 X X X
per clock
X X X

Table 7-3. Output Pixel Transfer Modes

G(0) B(1) B(0) R(7) R(6) R(5) R(4)
G(4) B(3) B(2) R(4) R(3) R(2) R(1)
G(2) B(3) P(2) R(4) R(3) R(2) R(1)
X X X R(7) R(6) R(5) R(4)
X X X R(4) R(3) R(2) R(1)
X X X R(4) R(3) R(2) R(1)
P0(20) P0(12) P0(4)
P1(23) P1(22) P1(21) P1(15)
R0(4) G0(4) B0(4)
R1(7) G1(6) G1(5) G1(7)
* * *
Upper Upper Upper
Lower Lower Lower Lower
P(20) P(12) P(4)
P(23) P(22) P(21) P(15)
R(4) G(4) B(4)
R(7) R(6) R(5) G(7)
* * *
P2(6) P1(14) P1(6) P0(14) P0(6) P3(22)
P3(23)
B2(6) G1(6) B1(6) G0(6) B0(6) R3(6)
R3(7)
* * * * * *
Upper Lower Lower Upper Upper Lower
Lower
P1(6) P0(14) P0(6) P0(14) P0(6) P1(22)
P1(23)
B1(6) G0(6) B0(6) G0(6) B0(6) R1(6)
R1(7)
* * * * * *
P4(23) P3(23) P2(23) P1(23) P0(23) P7(15) P7(7)
R4 R3 R2 R1 R0 G7 B7
* * * * * * *
Upper Lower Upper Lower Upper Lower Lower
P2(23) P1(23) P1(23) P0(23) P0(23) P3(15) P3(7)
R2 R1 R1 R0 R0 G3 B3
* * * * * * *
X X X X X X X
X X X X X X X
X X X X X X X
R(3) R(2) G(7) G(6) G(5) G(4) G(3)
R(0) R(4) G(5) G(4) G(3) G(2) G(1)
R(0) R(4) G(4) G(3) G(2) G(1) G(0)
R(2)
R(3) G(7) G(6) G(5) G(4) G(3)
*
R(4)
R(0) G(5) G(4) G(3) G(2) G(1)
*
R(4)
R(0) G(4) G(3) G(2) G(1) G(0)
*
P1(14) P1(13) P1(7) P1(6) P1(5) P0(23) P0(22)
G1(6) G1(5) B1(7) B1(6) B1(5) R0(7) R0(6)
Lower Lower Lower Lower Lower Upper Upper
P(14) P(13) P(7) P(6) P(5) P(23) P(22)
G(6) G(5) B(7) B(6) B(5) R(7) R(6)
P2(22)
P3(15) P3(7) P2(23) P2(15) P2(7) P1(23)
R2(6)
G3(7) B3(7) R2(7) G2(7) B2(7) R1(7)
*
Upper
Lower Lower Upper Upper Upper Lower
P1(22)
P1(15) P1(7) P1(23) P1(15) P1(7) P0(23)
R1(6)
G1(7) B1(7) R1(7) G1(7) B1(7) R0(7)
*
P6(15) P6(7) P5(15) P5(7) P4(15) P4(7) P3(15)
G6 B6 G5 B5 G4 B4 G3
* * * * * * *
Upper Upper Lower Lower Upper Upper Lower
P3(15) P3(7) P2(15) P2(7) P2(15) P2(7) P1(15)
G3 B3 G2 B2 G2 B2 G1
* * * * * * *
X X X X X X G2
X X X X X X B5
X X X X X X R7
G(2) B(7) B(6) B(5) B(4) B(3) B(2)
G(0) B(4) B(3) B(2) B(1) B(0) B(4)
G(4) B(4) B(3) B(2) B(1) B(0) B(4)
G(2) B(2)
B(7) B(6) B(5) B(4) B(3)
* *
G(0) B(4)
B(4) B(3) B(2) B(1) B(0)
* *
G(4) B(4)
B(4) B(3) B(2) B(1) B(0)
* *
P0(21) P0(15) P0(14) P0(13) P0(7) P0(6) P0(5)
R0(5) G0(7) G0(6) G0(5) B0(7) B0(6) B0(5)
Upper Upper Upper Upper Upper Upper Upper
P(21) P(15) P(14) P(13) P(7) P(6) P(5)
R(5) G(7) G(6) G(5) B(7) B(6) B(5)
P1(22) P0(22)
P1(15) P1(7) P0(23) P0(15) P0(7)
R1(6) R0(6)
G1(7) B1(7) R0(7) G0(7) B0(7)
* *
Lower Upper
Lower Lower Upper Upper Upper
P0(22) P0(22)
P0(15) P0(7) P0(23) P0(15) P0(7)
R0(6) R0(6)
G0(7) B0(7) R0(7) G0(7) B0(7)
* *
P3(7) P2(15) P2(7) P1(15) P1(7) P0(15) P0(7)
B3 G2 B2 G1 B1 G0 B0
* * * * * * *
Lower Upper Upper Lower Lower Upper Upper
P1(7) P1(15) P1(7) P0(15) P0(7) P0(15) P0(7)
B1 G1 B1 G0 B0 G0 B0
* * * * * * *
B2 R1 G1 B1 R0 G0 B0
R4 G4 B4 R3 G3 B3 R2
G7 B7 R6 G6 B6 R5 G5