Dspsc Register - Cirrus Logic EP93 Series User Manual

MaverickCrunch Co-Processor
EP93xx User's Guide
3

3.3 DSPSC Register

63 62
47 46
31 30
DAID
15 14
V FWDEN Invalid
Default:
Definition:
Bit Descriptions:
3-10
cfldrs c3, [r2], #4
cfmuls c1, c2, c3
cfadds c0, c0, c1
subs r12, r12, #4
bne inner_loop
sub r0, r3
cfstrs c0, [r0], #4
sub r2, r3
subs r1, r1, #4
bne outer_loop
mov pc, lr
61 60 59 58
45 44 43 42
29 28 27 26
HVID
13 12 11 10
Denorm RM[1:0]
0x0000_0000_0000_0000
MaverickCrunch Status and Control Register. Accessed only via the
MaverickCrunch instruction set. All bits, including status bits, are both
readable and writable. This register should generally be written only using a
read-modify-write sequence.
RSVD:
INST:
Copyright 2007 Cirrus Logic
; c3 = *filter++;
; c1 = c2 * c3;
; sum += c1;
; j -= 4;
; branch if j != 0
; *data++ = sum;
; n -= 4;
; branch if n != 0
57 56 55 54
INST
41 40 39 38
INST
25 24 23 22
RSVD ISAT UI
9 8 7 6
IXE UFE OFE RSVD IOE
Reserved. Unknown During Read.
Exception Instruction. Whenever an unmasked exception
occurs, these 32 bits are loaded with the instruction that
caused the exception. Hence, this contains the instruction
that caused the most recent unmasked exception.
; data -= m * 4;
; filter -= m * 4;
; return to caller
53 52 51 50
37 36 35 34
21 20 19 18
INT AEXC SAT[1:0]
5 4 3 2
IX UF OF
49 48
33 32
17 16
FCC[1:0]
1 0
RSVD IO
DS785UM1