Cirrus Logic EP93 Series User Manual page 425

Offset
Channel Base Address + 0x0028
Channel Base Address + 0x002C
Channel Base Address + 0x0030
Channel Base Address + 0x0034
Channel Base Address + 0x0038
Channel Base Address + 0x003C
CONTROL
31 30 29 28
PWSC
15 14 13 12
ETDP TM SAH
Address:
Channel Base Address + 0x0000 - Read/Write
Definition:
This is the Channel Control Register. Used to configure the DMA M2M
Channel. All control bits should be programmed before the ENABLE bit is set.
Bit Descriptions:
RSVD:
STALLIntEn:
SCT:
DS785UM1
Table 10-8. PPALLOC Register Reset Values (Continued)
Name
SAR_CURRENT1
DAR_BASE0
DAR_BASE1
DAR_CURRENT0
Reserved
DAR_CURRENT1
Note:See Table 10-3 for Channel Base Addresses
Note:* Write this location once to clear the bit (see Interrupt/Status register description
for which bits this rule applies to).
27 26 25 24
NO_HDSK
11 10 9 8
DAH PW
Reserved. Unknown During Read.
Setting this bit to "1" enables the generation of the STALL
interrupt in the STALL State of the DMA Channel State
machine. Setting this bit to "0" disables generation of the
STALL Interrupt.
Source Copy Transfer. This bit is used to set up a block
transfer from 1 memory source location. If SCT = 1, then
one word is read from the source memory location and
copied to a block of memory (the number of destination
locations written to is determined by BCR). If SCT = 0 then
the source address increments as normal after each
successful transfer as determined by the transfer size (this
is the default setting). In order to use this feature the
SAR_BASEx and DAR_BASEx registers must contain
word-aligned addresses - the DMA will ignore the 2 LSB's
Copyright 2007 Cirrus Logic
Access Bits
RO 32
R/W 32
R/W 32
RO 32
RO 32
23 22 21 20
RSS NFBintEn DREQP
7 6 5 4
BWC START ENABLE
DMA Controller
EP93xx User's Guide
Reset Value
0
0
0
0
0
19 18 17 16
RSVD DACKP ETDP
3 2 1 0
DONEIntEn SCT STALLIntEn
10-31
10