Cirrus Logic EP93 Series User Manual page 784

IDE Interface
EP93xx User's Guide
IDEDataIn
31 30
15 14
27
Address:
Default:
Definition:
Bit Descriptions:
IDEMDMADataOut
31 30
15 14
Address:
Default:
Definition:
27-14
29 28 27 26
13 12 11 10
0x800A_0014 - Read Only
0x0000_0000
In PIO mode read operation, this register is the Input Data Registers,
containing the register contents or the data read from the device. The register
is loaded from the DD pins at the positive edge of the DIORn signal. The
register is read only in this operation. In MDMA and UDMA data-in operations,
this register is an exact copy of the data in the input buffer to be transferred
through DMA. The register is read only in these operations. Any write to this
register is ignored.
IDEDD:
29 28 27 26
13 12 11 10
0x800A_0018 - Write Only (should be written by the DMA controller only)
0x0000_0000
In MDMA data-out operations, this register contains the data in the output
buffer to be transferred to the device. The data is written into this register by
the DMA controller. This register should only be addressed and written by the
Copyright 2007 Cirrus Logic
25 24 23 22
IDEDD
9 8 7 6
IDEDD
IDE input data in PIO read, data in input buffer in MDMA
and data at the head of input buffer in UDMA mode.
25 24 23 22
IDEDD
9 8 7 6
IDEDD
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1