Cirrus Logic EP93 Series User Manual page 365

Definition:
Global Interrupt Status Register
Bit Descriptions:
RSVD:
INT:
GlIntMsk
31 30 29 28
15 14 13 12
INT
Address:
0x8001_0064 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Global Interrupt Mask Register. This register is used to mask the GlIntSts bit,
to allow of block interrupts to the processor.
Bit Descriptions:
RSVD:
INT:
DS785UM1
Reserved. Unknown During Read.
Global interrupt bit. This bit is set whenever the MACint
signal to the interrupt controller is active. Writing a one to
this bit location will clear this bit until a new interrupt
condition occurs.
27 26 25 24
RSVD
11 10 9 8
Reserved. Unknown During Read.
Global interrupt mask bit. When set, any interrupt enabled
by the Interrupt Enable Register will set the Global
Interrupt Status interrupt bit. When clear, no interrupts will
reach the processor.
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
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RSVD
EP93xx User's Guide
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3 2 1 0
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