Cirrus Logic EP93 Series User Manual page 438

DMA Controller
EP93xx User's Guide
Bit Descriptions:
10
DAR_CURRENTx
31 30
15 14
Address:
Definition:
Bit Descriptions:
DMAGlInt
31 30
15 14
RSVD
10-44
SAR_CURRENTx: Returns the current value of the channel source address
29 28 27 26
13 12 11 10
DAR_CURRENT0: Channel Base Address + 0x0044 - Read Only
DAR_CURRENT1: Channel Base Address + 0x003C - Read Only
This is the Channel Current Destination Address Register.
DAR_CURRENTx: Returns the current value of the channel destination
29 28 27 26
13 12 11 10
D11 D10
Copyright 2007 Cirrus Logic
pointer. Upon writing the BCRx register, the contents of the
SAR_BASEx register is loaded into the SAR_CURRENTx
register and the x buffer becomes active. Following
completion of a transfer from a buffer, the post-
incremented address is stored in this register so that a
software service routine can detect the point in the buffer
at which transfer was terminated.
25 24 23 22
DAR_CURRENTx
9 8 7 6
DAR_CURRENTx
address pointer. Upon writing the BCRx register the
contents of the DAR_BASEx register is loaded into the
DAR_CURRENTx register and the x buffer becomes
active. Following completion of a transfer from a buffer, the
post-incremented address is stored in this register so that
a software service routine can detect the point in the buffer
at which transfer was terminated.
25 24 23 22
RSVD
9 8 7 6
D9 D8 D7 D6
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
D5 D4 D3 D2
17 16
1 0
17 16
1 0
D1 D0
DS785UM1