Cirrus Logic EP93 Series User Manual page 687

rx2_fifo_empty:
rx2_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
I2SGlCtrl
31 30 29 28
15 14 13 12
Address:
0x8082_000C - Read/Write
Default:
0x0000_0000
Definition:
2
I
Bit Descriptions:
RSVD:
i2s_ife:
i2s_loopback:
2
The I S global register deals with enabling the block and whether loopback mode is used.
2
The I S enable bit determines whether the PCLK is turned on for the I
for the data registers can be written without the I
clock cycles when writing to any of the control status registers.
2
When the I S controller is required to transmit or receive data, PCLK must be turned on via
this register.
2
The I S controller loopback mode bit determines if TX channel 0 is connected to RX channel
0. This will allow data be sent in a loop fashion from the transmitter back through the receiver.
This applies to all channels, with TX1 looped to RX1, and TX2 looped to RX2. When
loopback is active, data at the receiver input is ignored and transmit data is sent out normally.
The transmit section will control the clock configuration during loopback the same as if full-
duplex operation was used.
DS785UM1
when = 1, FIFO is empty, otherwise not empty
27 26 25 24
11 10 9 8
RSVD
S Global Control Register
Reserved. Unknown During Read.
Defines if I
for the I
0 - PCLK is off.
1 - PCLK is on.
Defines loopback operation.
0 - not in loopback mode
1 - Loopback mode selected.
Copyright 2007 Cirrus Logic
23 22 21 20
RSVD
7 6 5 4
2
S controller is enabled and PCLK is turned on
2
S controller.
2
S PCLK enabled. The ARM provides its own
2
I S Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
i2s_loopback i2s_ife
2
S. All registers except
21-31
21