Figure 21-1. Architectural Overview Of The I - Cirrus Logic EP93 Series User Manual

21.1 Introduction
2
The I S controller is used to stream serial audio data between the external I
ADCs/DACs, and the ARM Core. It consists of 3 transmitter channels and 3 receiver
channels. Each channel handles a single stereo stream. The transmitter and receiver are
completely independent of each other and are programmed separately. Each channel (RX
and TX) has its own set of addressable registers which allows access through the ARM APB
or DMA accesses.
Figure 21-1 gives an architectural overview of the I
controller.input and output signals.
The i2s_audioclk_mux section performs gating on the incoming audio clocks based on the
settings within the TX and RX clock configuration registers and delivers a known clock
definition to the rest of the I
DMA
Controller
DS785UM1
2
S controller.
Memory
I
2
S
6 DMA Channels
I2S_APB/
ARM
DMA IF
Core
AMBA APB
BUS
lrck
sck

Figure 21-1. Architectural Overview of the I

Copyright 2007 Cirrus Logic
21I
2
S controller. Table 21-1
TX Channel 0
TX Channel 1
TX Channel 2
lrckt & sckt to
each TX channel
RX Channel 0
RX Channel 1
RX Channel 2
lrckr & sckr
to each RX
channel
I2S_AudioClk_Mux
2
S Controller
Chapter 21
2
S Controller
2
S CODECs',
2
lists the I S
sdo0
sdo1
sdo2
sdi0
sdi1
sdi2
21-1
21