Internal M2P/P2M Channel Register Map; Table 10-4. Internal M2P/P2M Channel Register Map - Cirrus Logic EP93 Series User Manual

ARM920T Address
0x8000_0340 -> 0x8000_037C
0x8000_0380
0x8000_03C0
0x8000_03C4 -> 0x8000_FFFC

10.2.2 Internal M2P/P2M Channel Register Map

The DMA Memory Map above includes the base address mapping for the channel registers
for each of the 10 M2P/P2M channels that are shown in the following table, the Internal
M2P/P2M Channel Register Map. This mapping is common for each channel thus offset
addresses from the bases in
Offset
Channel Base Address + 0x0000
Channel Base Address + 0x0004
Channel Base Address + 0x0008
Channel Base Address + 0x000C
Channel Base Address + 0x0010
Channel Base Address + 0x0014
Channel Base Address + 0x0018
Channel Base Address + 0x001C
Channel Base Address + 0x0020
Channel Base Address + 0x0024
Channel Base Address + 0x0028
Channel Base Address + 0x002C
Channel Base Address + 0x0030
Channel Base Address + 0x0034
Channel Base Address + 0x0038
Channel Base Address + 0x003C
DS785UM1
Table 10-3. DMA Memory Map
Description
M2P Channel 8 Registers (Tx)
DMA Channel Arbitration
register
DMA Global Interrupt register
Not Used
Table 10-3 are shown in

Table 10-4. Internal M2P/P2M Channel Register Map

Register
Name
"CONTROL"
"INTERRUPT"
"PPALLOC"
"STATUS"
Reserved
"REMAIN"
Reserved
Reserved
"MAXCNTx"
"BASEx"
"CURRENTx"
Reserved
"MAXCNTx"
"BASEx"
"CURRENTx"
Reserved
Note:See Table 10-3 for Channel Base Addresses
Note:* - write this location once to clear the interrupt (see Interrupt register description
for which bits this rule applies to).
Copyright 2007 Cirrus Logic
Channel Base Address
0x8000_0340
0x8000_03C4
Table 10-4.
Access Bits Reset Value
R/W 6
R/W TC * 3
Channel dependant
R/W 4
(see register description)
RO 8
RO 16
R/W 16
R/W 32
RO 32
R/W 16
R/W 32
RO 32
DMA Controller
EP93xx User's Guide
0
0
0
0
0
0
0
0
0
0
10-21
10