Cirrus Logic EP93 Series User Manual page 391

RXDThrshld
31 30 29 28
15 14 13 12
Address:
0x8001_00E0 - Read/Write
Suggested Value:
0x0004_0002
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Descriptor Threshold register. The receive descriptor thresholds are
used to set a limit on the amount of empty space allowed in the MAC's receive
descriptor FIFO before a bus request will be scheduled. When the number of
empty words in the FIFO exceeds the threshold value, the Descriptor
Processor will schedule a bus request to transfer descriptors. The actual
posting of the bus request may be delayed due to lack of resources in the
MAC, such as a RXDEnq equal to zero. The lower two bits of the thresholds
are always zero.
Bit Descriptions:
RSVD:
0:
RDHT:
DS785UM1
The hard and soft threshold work in exactly the same
manner except one. The soft threshold will not cause a
bus request to be made if the bus is currently in use, but
only when it is deemed to be idle (no transfers for four
AHB clocks). The hard threshold takes effect immediately
regardless of the state of the bus. This operation allows for
more efficient use of the AHB bus by allowing smaller
transfers to take place when the bus is lightly loaded and
requesting larger transfers only when the bus is more
heavily loaded.
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read.
Must be written as "0".
Receive Status Hard Threshold.
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
23 22 21 20
RDHT
7 6 5 4
RDST
EP93xx User's Guide
19 18 17 16
0 0
3 2 1 0
0 0
9-89
9