Cirrus Logic EP93 Series User Manual page 708

AC'97 Controller
EP93xx User's Guide
AC97IM
31 30
15 14
22
Address:
Definition:
AC97EOI
31 30
15 14
Address:
22-20
29 28 27 26 25
13 12 11 10
RSVD
0x8088_0094 - Read/Write
Controller Interrupt Enable Register. The AC'97 Controller interrupt enable
register is a read/write register that controls the interrupt enables for the
interrupts outside the FIFO channels.
Bit Descriptions:
RSVD:
SLOT2TXCOMPLETE:If this bit is set to "1", the SLOT2TXCOMPLETE
CODECREADY:
WINT:
GPIOINT:
GPIOTXCOMPLETE:If this bit is set to "1", the GPIOTXCOMPLETE interrupt
SLOT2RXVALID: If this bit is set to "1", SLOT2RXVALID interrupt is enabled.
SLOT1TXCOMPLETE:If this bit is set to "1", SLOT1TXCOMPLETE interrupt is
29 28 27 26
13 12 11 10
0x8088_0098 - Write Only
24 23 22
RSVD
9 8 7 6
SLOT2TX
COMPLETE
Reserved. Unknown During Read.
interrupt is enabled.
If this bit is set to "1", the Codec Ready Interrupt is
enabled.
If this bit is set to "1", the Wake-up Interrupt is enabled.
If this bit is set to "1", the GPIO interrupt is enabled.
is enabled.
enabled.
25 24 23 22
9 8 7 6
RSVD
Copyright 2007 Cirrus Logic
21 20 19 18
5 4 3 2
CODEC WINT GPIO GPIOTX
READY INT COMPLETE
21 20 19 18
5 4 3 2
17 16
1 0
SLOT2RX SLOT1TX
VALID COMPLETE
17 16
1 0
CODECREADY WINT
DS785UM1