Cirrus Logic EP93 Series User Manual page 362

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
IntStsP/IntStsC
9
31 30
RSVD RWI
15 14
RSVD
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
9-60
29 28 27 26
RxMI RxBI RxSQI TxLEI
13 12 11 10
MIII PHYSI TI
0x8001_0028, for IntStsP - Read/Write
0x8001_002C, for IntStsC - Read Only
0x0000_0000
0x0000_0000
Interrupt Status Preserve and Clear Registers. The interrupt status bits are set
when the corresponding events occur in the MAC. If the corresponding
interrupt enable bit is set in the interrupt enable register, an interrupt signal will
be generated.
Interrupt status is available at two different offsets: Interrupt Status Preserve
and Interrupt Status Clear. Both offsets are a read of the same storage.
Reading the Interrupt Status register Preserve has no effect on the status in
the register, but writing a 1 to a location in this register clears the status bit,
writing a zero has no effect. Reading the Interrupt Status Clear register clears
all the bits in the register that are accessed as defined by the AHB HSIZE
signal. Therefore a routine which will handle all reported status may read via
the Interrupt Status Clear thereby saving a write operation.
RSVD:
RWI:
Copyright 2007 Cirrus Logic
25 24 23 22
ECI TxUHI
9 8 7 6
AHBE SWI RSVD
Reserved. Unknown During Read.
Remote Wake-up Interrupt. The remote wake status is set
when a remote wake-up frame is received, and the
RemoteWakeEn (RXCtl) is set. A remote wake-up frame
must pass the receive destination address filter and have
a contiguous sequence of 6 bytes of FFh followed by 8
repetitions of the Individual Address and be a legal frame
(legal length and good CRC).
21 20 19 18
RSVD MOI
5 4 3 2
OTHER TxSQ RxSQ
17 16
TxCOI RxROI
1 0
RSVD
DS785UM1