Cirrus Logic EP93 Series User Manual page 155

SWRST:
VidClkDiv
31 30 29 28
15 14 13 12
VENA ESEL PSEL
Address:
0x8093_0084 - Read/Write, Software locked
Default:
0x0000_0000
Definition:
Configures video clock for the raster engine. Selects input to VCLK dividers
from either PLL1 or PLL2, and defines a programmable divide value.
Bit Descriptions:
RSVD:
VENA:
ESEL:
PSEL:
PDIV:
VDIV:
DS785UM1
Software reset. A one to zero transition of this bit initiates
a software reset.
27 26 25 24
RSVD
11 10 9 8
RSVD PDIV
Reserved. Unknown During Read.
Enable VCLK divider.
External clock source select.
0 - use the external XTALI clock input as the clock source.
1 - use one of the internal PLLs selected by PSEL as the
clock source.
PLL source select.
1 - select PLL2 as the clock source.
0 - select PLL1 as the clock source.
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
VCLK divider value. Forms a divide-by-N of the pre-divide
clock output. VCLK is the source clock divided by PDIV
divided by N. Must be at least two.
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
RSVD
System Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
VDIV
5-29
5