Ide Package Dependency; System Configuration Constraints; Bus Bandwidth Requirements; Table 27-5. Maximum Theoretical Bandwidths For Various Operating Modes - Cirrus Logic EP93 Series User Manual

27.2.7.3.3 Ultra DMA Read from IDE Controller
Follow the wait-state number listed in the wait-state table in
However, the DMA request will not assert unless there are 4 words present in the read FIFO
or the transfer is non-quad aligned and has the last remaining bits of data, so quad-word
bursts are permissible if the total Ultra DMA transfer size is quad-word aligned.
27.2.7.3.4 Ultra DMA Write to IDE Controller
Although the DMA request line has a non-insignificant DMAIDE latency, the DMA write FIFO
is of sufficient size to absorb any overage incurred during the DMA request latency period.
The DMA controller can be run without wait-states. Quad-word bursts are permissible if the
Ultra DMA transfer size is quad-word aligned.

27.2.8 IDE Package Dependency

The block uses the following external pins:
IDECS0n, IDECS1n, IDEDA, DIORn, DIOWn, DMACKn, DD, IORDY, INT[3], EGPIO[2],
and EGPIO[15].

27.2.8.1 System Configuration Constraints

The following system configuration modes force the disabling of the IDE controller:
- GPIOEonIDE
- GPIOFonIDE
- GPIOGonIDE
- GPIOHonIDE

27.2.8.2 Bus Bandwidth Requirements

The block does not have any hard bandwidth constraints because it can throttle performance
to the available bandwidth without data corruption. The maximum free bandwidth that the
block will consume is limited by the IDE mode the device is in. Maximum theoretical
bandwidths are listed in

Table 27-5. Maximum Theoretical Bandwidths for Various Operating Modes

Mode
PIO Mode 0
PIO Mode 1
PIO Mode 2
PIO Mode 3
PIO Mode 4
MDMA Mode 0
MDMA Mode 1
MDMA Mode 2
DS785UM1
Table 27-5.
MAX IDE Device Bandwidth
Copyright 2007 Cirrus Logic
Table 27-3 and
3.33 MBps
5.22 MBps
8.33 MBps
11.11 MBps
16.67 MBps
4.17 MBps
13.33 MBps
16.67 MBps
IDE Interface
EP93xx User's Guide
Table 27-4.
27
27-9