Cirrus Logic EP93 Series User Manual page 587

TIS:
RIS:
MIS:
UART3LowPwrCntr
31 30 29 28
15 14 13 12
Address:
0x808E_0020 - Read/Write
Default:
0x0000_0000
Definition:
UART3 IrDA Low Power Divisor Register. This register is present in UART3
but is not supported.
Bit Descriptions:
RSVD:
UART3DMACtrl
31 30 29 28
15 14 13 12
Address:
0x808E_0028 - Read/Write
DS785UM1
Transmit Interrupt Status. This bit is set to 1 if the
UARTTXINTR transmit interrupt is asserted, which occurs
when the transmit FIFO is not full. It is set to 0 when the
transmit FIFO is full.
Receive Interrupt Status. This bit is set to 1 if the
UARTRXINTR receive interrupt is asserted, which occurs
when the receive FIFO is not empty. It is set to 0 when the
receive FIFIO is empty.
Modem Interrupt Status. This bit is set to 1 if the
UARTMSINTR modem status interrupt is asserted. This
bit is cleared by writing any value to this register.
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read.
27 26 25 24
RSVD
11 10 9 8
RSVD
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
23 22 21 20
7 6 5 4
UART3 With HDLC Encoder
EP93xx User's Guide
19 18 17 16
3 2 1 0
19 18 17 16
3 2 1 0
DMAERR TXDMAE RXDMAE
16-11
16