Instruction Set For The Maverickcrunch Co-Processor; Table 3-8. Mcr Opcode Map; Table 3-9. Mrc Opcode Map - Cirrus Logic EP93 Series User Manual

op cp
code1 num
[3:0]
000
0100 cfmvdlr
0 0101 cfmv64lr
0110
op cp
code1 num
[3:0]
000
0100 cfmvrdl
0 0101 cfmvr64l
0110

3.5 Instruction Set for the MaverickCrunch Co-Processor

Table 3-10 summarizes the MaverickCrunch co-processor instruction set. Please note that:
• CRd, CRn, and CRm each refer to any of the 16 general purpose MaverickCrunch
registers unless otherwise specified
• CRa refers to any of the MaverickCrunch accumulators
• Rd and Rn refer to any of the 16 general purpose ARM920T registers
• <imm> refers to a seven-bit immediate value
The remainder of this section describes in detail each of the individual MaverickCrunch
instructions. The fields in the opcode for each MaverickCrunch instruction are shown. When
specific bit values are required for the instruction, they are shown as either '1' or '0'. Any field
whose value may vary, such as a register index, is named as in the ARM programming
manuals, and its function described below.
DS785UM1

Table 3-8. MCR Opcode Map

001 010
cfmvdhr cfmvsr
cfmv64hr cfrshl32 cfrshl64

Table 3-9. MRC Opcode Map

001 010
cfmvrdh cfmvrs
cfmvr64h
Copyright 2007 Cirrus Logic
opcode2[2:0]
011 100 101
opcode2[2:0]
011 100 101
cfcmps cfcmpd
cfcmp32 cfcmp64
MaverickCrunch Co-Processor
EP93xx User's Guide
110 111
110 111
3
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