Pixelmode; Blink Logic; Blinkrate; Defining Blink Pixels - Cirrus Logic EP93 Series User Manual

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
7

7.4.10.2 PixelMode

Pixel data is transferred from the FIFO to the Video Pixel Mux two 32-bit words at a time (total
of 64 bits). Bits[2:0] of the
11. The Video Pixel MUX uses the
contained in the 64 bits of data. The Video Pixel Mux extracts pixel data from the 64-bits and
passes that pixel data to the BLINK logic one pixel at a time.
Note: All other combinations for these three bits are illegal.

7.4.11 Blink Logic

The blink logic facilitates blinking of individual pixels as they move through the video pipeline.
The blink frequency is controlled by the
same rate.

7.4.11.1 BlinkRate

This value is used to control the number of video frames that occur before the pixel value that
is assigned to blink is switched between its non-blinked and blinked values. The actual rate is
calculated by:
Blink cycle = 2 x (1 / VCLK) x HClkTotal x VLinesTotal x (255 - BlinkRate)

7.4.11.2 Defining Blink Pixels

A blink pixel must be defined before the blink logic is applied to a given pixel. The
"BlinkPattrn"
7-32
VLineStep = 640 x 4bpp/32
"PixelMode"

Table 7-11. Bits P[2:0] in the PixelMode Register

bit P2 bit P1
0 0
0 0
0 1
1 0
1 1
where:
VCLK is the basic clock rate of the video logic
HClkTotal is the value contained in the
VLinesTotal is the value contained in the
BlinkRate is the value contained in the
and "PattrnMask"
register specify the pixel depth as shown in
"PixelMode" register to determine how many pixels are
bit P0
0 Pixel Multiplexor disabled
1 4 bits per pixel
0 8 bits per pixel
0 16 bits per pixel
0 24 bits per pixel
"BlinkRate" register. All blinking pixels blink at the
"HClkTotal"
"VLinesTotal"
"BlinkRate"
registers are used to define the blink pixels.
Copyright 2007 Cirrus Logic
Function
register
register
register
Table 7-
DS785UM1