Table 21-1. I 2 S Controller Input And Output Signals; Table 21-2. Audio Interfaces Pin Assignment - Cirrus Logic EP93 Series User Manual

2
I S Controller
EP93xx User's Guide
21
The primary I
SSP pins or the Ac97 pins. The second and third I
primary I
second I
EGPIO[5] respectively and are enabled by setting DeviceCfg.A1onG. The third I
serial output and serial input pins are multiplexed with EGPIO[6] and EGPIO[13] respectively
and are enabled by setting DeviceCfg.A2onG.
2
21.2 I S Transmitter Channel Overview
Each I
can operate in master or slave mode. Data is transferred between the ARM Core and the I
controller via an interrupt based mechanism or DMA access. The ARM Core or host
processor must write words in multiples of 2 (that is, a left and right stereo pair). These words
are serially shifted out, timed with respect to the audio bit clock and word clock (SCLK and
LRCK) that are generated (see
The key features of the I
• Three transmit data channels, master or slave mode.
21-2
Table 21-1. I
Signal Name
lrck
sck
sdi0
sdi1
sdi2
sdo0
sdo1
sdo2
2
S port and the I
2
S port, but their serial output and input pins are multiplexed with EGPIO pins. The
2
S port's serial output and serial input pins are multiplexed with EGPIO[4] and

Table 21-2. Audio Interfaces Pin Assignment

Normal Mode
Pin
Name
Pin Description
SCLK1 SPI Bit Clock
SFRM1 SPI Frame Clock
SSPRX1 SPI Serial Input
SSPTX1 SPI Serial Output
ARSTn AC'97 Reset
ABITCLK AC'97 Bit Clock
ASYNC AC'97 Frame Clock
ASDI AC'97 Serial Input
ASDO AC'97 Serial Output
2
S TX channel provides a single stereo I
2
S transmitter are:
2
S Controller Input and Output Signals
Type
IN Left/right Word Audio slave clock.
IN Audio bit slave clock.
IN Serial data for channel 0
IN Serial data for channel 1
IN Serial data for channel 2
OUT Serial data output for TX channel 0
OUT Serial data output for TX channel 1
OUT Serial data output for TX channel 2
2
S clocks are multiplexed and can be assigned to either the
2
S ports use the same clock pins as the
2
I S on SSP Mode
Pin Description
2
I S Serial Clock
2
I S Frame Clock
2
I S Serial Input
2
I S Serial Output
2
(No I S Master Clock)
AC'97 Reset
AC'97 Bit Clock
AC'97 Frame Clock
AC'97 Serial Input
AC'97 Serial Output
2
S compliant output. The Transmit channel
Chapter 5, "Clock Control" on page 5-4
Copyright 2007 Cirrus Logic
Description
2
S port's
2
I S on AC'97 Mode
Pin Description
SPI Bit Clock
SPI Frame Clock
SPI Serial Input
SPI Serial Output
2
I S Master Clock
2
I S Serial Clock
2
I S Frame Clock
2
I S Serial Input
2
I S Serial Output
for additional details).
2
S
DS785UM1