Memory Map; Table 2-7. Global Memory Map For The Two Boot Modes - Cirrus Logic EP93 Series User Manual

ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User's Guide
2

2.3.5 Memory Map

The memory map for Synchronous Memory Boot and Asynchronous Memory Boot is shown
in Table
If internal Boot Mode is selected and the register BootModeClr has been written, the address
range 0x0000_0000 -> 0x0000_FFFF is occupied by the internal Boot ROM until the internal
Boot Code is completed. After boot completion, either Synchronous or Asynchronous
memory is re-mapped to occupy this address space.
NOTE: Some memory locations are listed as Reserved. These memory locations should not
be used. Reading from these memory locations will yield invalid data. Writing to these
memory locations may cause unpredictable results.
2-16
Table 2-6. CP15 ARM920T Register Description (Continued)
Register
11,12,14
Reserved
FCSE PID Register: (Read/Write) ARM9TDMI core addresses ranging from 0 to 32MB are
13
translated by this register to A + FCSE*32MB and then sent to the MMU. If turned off,
straight addresses are sent to the MMU.
15
Test Register Only: Reads or writes will cause unpredictable behavior.
2-7.

Table 2-7. Global Memory Map for the Two Boot Modes

Address Range
0xF000_0000 - 0xFFFF_FFFF
0xE000_0000 - 0xEFFF_FFFF
0xD000_0000 - 0xDFFF_FFFF
0xC000_0000 - 0xCFFF_FFFF
0x9000_0000 - 0xBFFF_FFFF
0x8080_0000 - 0x8FFF_FFFF
0x8010_0000 - 0x807F_FFFF
0x8000_0000 - 0x800F_FFFF
0x7000_0000 - 0x7FFF_FFFF
0x6000_0000 - 0x6FFF_FFFF
0x5000_0000 - 0x5FFF_FFFF
0x4000_0000 - 0x4FFF_FFFF
0x3000_0000 - 0x3FFF_FFFF
0x2000_0000 - 0x2FFF_FFFF
0x1000_0000 - 0x1FFF_FFFF
0x0001_0000 - 0x0FFF_FFFF
0x0000_0000 - 0x0000_FFFF
Copyright 2007 Cirrus Logic
Description
Sync Memory Boot
ASD0 Pin = 1
Async memory (nCS0)
Sync memory (nSDCE2)
Sync memory (nSDCE1)
Sync memory (nSDCE0)
Not Used
APB mapped registers
Reserved
AHB mapped registers
Async memory (nCS7)
Async memory (nCS6)
Reserved
PCMCIA (Slot 0)
Async memory (nCS3)
Async memory (nCS2)
Async memory (nCS1)
Sync memory (nSDCE3)
Sync memory (nSDCE3)
or
Internal Boot ROM
if INTBOOT is selected
Async Memory Boot
ASD0 Pin = 0
Sync memory (nSDCE3)
Sync memory (nSDCE2)
Sync memory (nSDCE1)
Sync memory (nSDCE0)
Not Used
APB mapped registers
Reserved
AHB mapped registers
Async memory (nCS7)
Async memory (nCS6)
Reserved
PCMCIA (Slot 0)
Async memory (nCS3)
Async memory (nCS2)
Async memory (nCS1)
Async memory (nCS0)
Async memory (nCS0)
or
Internal Boot ROM
if INTBOOT is selected
DS785UM1