Cirrus Logic EP93 Series User Manual page 242

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
7
ParllIfOut
31 30
15 14
Address: 0x8003_0058
Default: 0x0000_0000
Definition: Parallel Interface Output/Control Register.
Bit Descriptions:
7-60
Table 7-16. Bits per Pixel Scanned Out (Continued)
P2 P1 P0
1 0 0
1 0 1
1 1 0
1 1 1
29 28 27 26
13 12 11 10
RSVD
This register, if PIFEN = '1' in the
Smart Panel. A Smart Panel has an integrated controller and frame buffer.
RSVD:
RD:
DAT:
Copyright 2007 Cirrus Logic
Pixel Mode
16 bits per pixel
do not use
24 bits per pixel packed
32 bits per pixel (24 bits per pixel unpacked)
25 24 23 22
RSVD
9 8 7 6
RD
VideoAttribs
Reserved - Unknown during read
Read control bit - Write Only
Writing a '0' to this bit location will initiate a parallel
interface write cycle; writing a '1' will initiate a parallel
interface read cycle:
1 - Start Smart Panel write cycle
0 - Start Smart Panel read cycle
Data - Write Only
The value written to this field is output on the parallel
interface pins during a write cycle. Writing PIFEN = '1' to
the VideoAttribs register redefines the signals on these
pins for Parallel Interface (Smart Panel) operation:
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
21 20 19 18
5 4 3 2
DAT
register, is used to access a
17 16
1 0
DS785UM1