Cirrus Logic EP93 Series User Manual page 372

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
9
BMSts
31 30
15 14
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
9-70
RxEn:
29 28 27 26
13 12 11 10
RSVD
0x8001_0084 - Read Only
0x0000_0000
0x0000_0000
Bus Master Status Register
RSVD:
TxAct:
TP:
Copyright 2007 Cirrus Logic
Receive Enable. Writing a one to Receive Enable causes
receive DMA transfers to be enabled. This is reflected in
RxAct (Bus Master Status) being set. This bit is an act-
once-bit and will clear automatically when the enable is
complete. The first time the RxEn bit is set following a
AHB reset, or a RxChRes, the MAC performs a receive
channel initialization. During this initialization the RXDEnq,
and RXStsEnq registers are cleared and the endpoints of
the Receive Descriptor and Status Queues are calculated.
When the initialization is complete, the RxAct (BMSts) is
set.
25 24 23 22
RSVD
9 8 7 6
TxAct RSVD
Reserved. Unknown During Read.
Transmit Active. When this bit is set, the channel is active
and may be in the process of transferring transmit data.
Following a TxDisable Command (Bus Master Control),
when transfers have been halted, this bit is cleared.
Transfer Pending. When the Manual Transfer bit (BMCtl) is
set, the Transfer Pending bit is set, until all internal FIFOs
have either been active for a DMA transfer, or have been
determined to be inactive (that is, empty transmit status
FIFO).
21 20 19 18
5 4 3 2
TP RxAct
17 16
1 0
QID
DS785UM1