Table 21-3. Transmitter Fifo's - Cirrus Logic EP93 Series User Manual

• Supports 16/24/32 bit word lengths.
• Programmable left/right word clock polarity on the serial frame.
• Programmable Bit Clock polarity.
• Programmable data validity, that is, data valid on the rising/negative edge of the bit
clock.
• Programmable first data bit position (I
• Programmable Left or Right data word justification
• Programmable data shift direction, that is, MSB or LSB transmitted first.
• Data underflow detection, that is, re-transmission of old data.
• Clock domain synchronization.
• DMA access.
Right Sample 7
7 Left Sample 7
Right Sample 6
:
:
Right Sample 0
1 Left Sample 1
Right Sample 0
0 Left Sample 0
Each channel has a 16 deep by 32bit wide FIFO where the ARM or DMA controller can write
up to 8 sets of left/right data pairs before enabling the channel for transmission. In order to fill
the FIFO the following sequence of events must be performed by the programmer. (NOTE:
The following discussion is with respect to 1 channel only but applies to all.)
2
1. Enable I S controller: The I
in order to turn on the PCLK to the I
correctly if this is not done.
2. Write to the FIFO: Once the I
either the DMA or the ARM.
Each FIFO is split up into 8 locations. Each location consists of 2 X 32bit register and
can hold one left and one right stereo sample (16, 24 or 32 bits per sample). For APB
accesses, the left and right samples must be written to different addresses: I2STX0Lft
register address for left samples and I2STX0Rt register address for right samples (see
register definitions).
In order to fill a FIFO location, the programmer must write two data words,
corresponding to left and right stereo data, to the FIFO. Only when both words are
written by the programmer will the FIFO be loaded. Assuming this is the first FIFO write,
DS785UM1
2
S or non-I

Table 21-3. Transmitter FIFO's

Byte 7
Byte 3
Byte 7
: :
: :
Byte 7
Byte 3
Byte 7
Byte 3
2
S global control register bit, I2SGlCtrl[0] must be written to
2
S controller. The I
2
S controller is enabled, the TX FIFO may be written to by
Copyright 2007 Cirrus Logic
2
S format).
Byte 6 Byte 5
Byte 2 Byte 1
Byte 6 Byte 5
: :
: :
Byte 6 Byte 5
Byte 2 Byte 1
Byte 6 Byte 5
Byte 2 Byte 1
2
S controller will not function
2
I S Controller
EP93xx User's Guide
21
Byte 4
Byte 0
Byte 4
:
:
Byte 4
Byte 0
Byte 4
Byte 0
21-3