Table 14-2. Legal Hdlc Mode Configurations - Cirrus Logic EP93 Series User Manual

UART1 With HDLC and Modem Control Signals
EP93xx User's Guide
The receiver utilizes a digital PLL to synchronize to the incoming encoded bit stream. The
digital PLL should always successfully lock on to an incoming data stream within two bytes
provided that the first two bits of the first byte are either "01" or "10". Hence, at a minimum,
two bytes must precede the final opening flag to insure that the HDLC receiver sees the
packet. To meet this requirement, the simplest approach is to insure that at least three
opening flags are received if the packet is Manchester encoded. (Note that to meet this
requirement when transmitting, field HDLC1Ctrl.FLAG should be set to 0010b.)
14
Three bits in various combination determine how an external or internal clock may be used
along with NRZ data. The clock will have a period equal to the bit period of the data stream,
and it is expected that the internal or external receiver will sample the bit at or near the rising
edge of this clock.
To generate an internal clock suitable for sending along with the transmitted data, set
UART1HDLCCtrl.TXCM and UART1HDLCCtrl.CMAS. To make the receiver use the same
internal clock, set UART1HDLCCtrl.RXCM. To make the receiver use an externally generated
clock, clear UART1HDLCCtrl.CMAS, but set UART1HDLCCtrl.RXCM.
To force the transmitter to use the same external clock, also set UART1HDLCCtrl.TXCM. The
clock is either internal or external, that is, the receiver cannot use an external clock while the
transmitter generates and sends an internal one. Refer to the documentation for the
DeviceCfg register in Syscon for the use and routing of HDLC clocks to or from external pins
on the device.
The internal clock is generated by the transmitter only while it is sending data or flags; the
clock is not generated while the transmitter is idle. For this reason, another transmitter which
expects to use this clock to at any time send its own packets cannot reliably do so. To insure
that a clock is continuously generated, the IDLE bit in the UART1HDLCCtrl register may be
set, which causes this transmitter to continuously send flags between packets instead of
going idle.
Table 14-2
CMAS TXCM RXCM TXENC RXENC SYNC
14-10
summarizes the legal HDLC mode configurations.

Table 14-2. Legal HDLC Mode Configurations

UART1HDLCCtrl Bits Set
- - - -
- - - -
- - - -
- - - 1
- - - 1
- - 1 -
- - 1 1
- 1 - -
- 1 - -
1 1 - -
Transmit Mode
- - Asynchronous NRZ
- 1 Synchronous NRZ
1 1 Synchronous NRZ
- 1 Manchester
1 1 Manchester
- 1 Synchronous NRZ
- 1 Manchester
- 1 External clock
1 1 External clock
- 1 Internal clock
Copyright 2007 Cirrus Logic
Receive Mode
Asynchronous NRZ
Synchronous NRZ
Manchester
Synchronous NRZ
Manchester
External clock
External clock
Synchronous NRZ
Manchester
Synchronous NRZ
DS785UM1