Cirrus Logic EP93 Series User Manual page 628

IrDA
EP93xx User's Guide
MISR
31 30
15 14
17
Address:
Default:
Definition:
Bit Descriptions:
17-32
29 28 27 26
13 12 11 10
RSVD
0x808B_0080 - Read/Write
0x0000_0000
MIR Status Register.
RSVD:
RFL:
RIL:
RFC:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
RFL
Reserved. Unknown During Read.
Receive Frame Lost. Set to a "1" when a ROR occurred at
the start of a new frame, before any data for the frame
could be put into the receive FIFO. This bit is cleared by
writing a "1" to this bit. This occurs if the last entry in the
FIFO already contains a valid EOF bit from a previous
frame when a FIFO overrun occurs. The ROR bit cannot
be placed into the FIFO and all data associated with the
frame is lost.
Receive Information Buffer Lost. Set to a "1" when the last
data for a frame is read from the receive FIFO and the
RFC bit is still set from a previous end of frame. This bit is
cleared by writing a "1" to this bit. This is triggered if the
RFC bit is already set before the last data from a frame is
read from the IrData register. It indicates that the data from
the IrRIB register was lost. This can occur if the CPU does
not respond to the RFC interrupt before another (short)
frame completes and is read from the IrData register by
the DMA controller.
Received Frame Complete. Set to "1" when the last data
for a frame is read from the receive FIFO (via the IrData
register). This event also triggers the IrRIB to load the
IrFlag and byte count. This bit is cleared when the IrRIB
register is read.
21 20 19 18
5 4 3 2
RIL RFC RFS TAB
17 16
1 0
TFC TFS
DS785UM1