Cirrus Logic EP93 Series User Manual page 785

DMA controller. A write by the host during MDMA data-out operation will
erroneously interfere with the MDMA state machine. Any read will return zero.
Bit Descriptions:
IDEDD:
IDEMDMADataIn
31 30 29 28
15 14 13 12
Address:
0x800A_001C - Read Only (should be read by the DMA controller only)
Default:
0x0000_0000
Definition:
In MDMA data-in operations, this register contains the data in the input buffer
just transferred from the device. The data is read from this register by the DMA
controller. This register should only be addressed and read by the DMA
controller. A read by the host during MDMA data-in operation will erroneously
interfere with the MDMA state machine. Any write is ignored.
Bit Descriptions:
IDEDD:
IDEUDMADataOut
31 30 29 28
15 14 13 12
Address:
0x800A_0020 - Write Only (should be written by the DMA controller only)
Default:
0x0000_0000
Definition:
In UDMA data-out operations, this register contains the data at the tail of the
output buffer to be written by the DMA controller. This register should only be
DS785UM1
IDE output data in the output buffer in MDMA mode.
27 26 25 24
IDEDD
11 10 9 8
IDEDD
IDE input data in the input buffer in MDMA mode.
27 26 25 24
IDEDD
11 10 9 8
IDEDD
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
23 22 21 20
7 6 5 4
IDE Interface
EP93xx User's Guide
19 18 17 16
3 2 1 0
19 18 17 16
3 2 1 0
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