Clocking Requirements; Table 14-4. Uart1 Pin Functionality; Table 14-5. Devicecfg Register Bit Functions - Cirrus Logic EP93 Series User Manual

PIN
RXD0 UART1 input pin
TXD0 UART1 output pin
CTSn Modem input: Clear To Send
DSRn Modem input: Data Set Ready (also used for DCDn Data Carrier Detect)
Modem input RIn: Ring Indicator if Syscon register DeviceCfg[25] MODonGPIO is set.
EGPIO[0]
Otherwise, RIn is driven low.
DTRn Modem output Data Terminal Ready if Syscon register TESTCR[27] RTConGPIO is clear.
RTSn Modem output: Ready To Send
EGPIO[3] HDLC clock
The use of EGPIO[3] is determined by several bits in Syscon register DeviceCfg. See
Table 14-5.
bit 14
HC3EN HC1IN
x
0
0

14.5.1 Clocking Requirements

There are two clocks, PCLK and UARTCLK.
UARTCLK frequency must accommodate the desired range of baud rates:
The frequency of UARTCLK must also be within the required error limits for all baud rates to
be used.
To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less
than or equal to four times the frequency of PCLK:
DS785UM1

Table 14-4. UART1 Pin Functionality

Table 14-5. DeviceCfg Register Bit Functions

bit 13 bit 12
HC1EN
0 x
1 1
0 1
≥
F
UARTCLK
MIN
≤
F 32
UARTCLK
MAX
F
UARTCLK
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
Description
Function
External HDLC clock input is driven low.
External HDLC clock input is driven by EGPIO[3].
Internal HDLC clock output drives EGPIO[3].
×
32 baudrate
MAX
× × audrate
65536 b
MIN
≤ ×
4 F
PCLK
EP93xx User's Guide
14
14-15