I 2 S Global Status Registers - Cirrus Logic EP93 Series User Manual

2
21.7.4 I S Global Status Registers
2
I S Global Status Registers
I2SGlSts
31 30 29 28
RSVD rx2_fif rx2_fifo
o_half_ _empty
full
15 14 13 12
rx0_fifo tx0_fifo tx0_fifo tx0_fifo
_full _half_ _empty _full
empty
Address:
0x8082_0008 - Read/Write
Default:
0x0001_2492
Definition:
UART Data Register
Bit Descriptions:
RSVD:
Tx0_underflow:
Tx1_underflow:
Tx2_underflow:
Rx0_overflow:
Rx1_overflow:
Rx2_overflow:
Tx0_overflow:
DS785UM1
27 26 25
rx2_fifo_f tx2_fifo_h tx2_fifo_e tx2_fifo_
ull alf_ mpty
empty
11 10 9
Rx2_ Rx1_ Rx0_ Tx2_
underflow underflow underflow overflow
Reserved. Unknown During Read.
when = 1, TX0 FIFO has underflowed.
when = 1, TX0 FIFO has underflowed.
when = 1, TX0 FIFO has underflowed.
when = 1, RX0 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
when = 1, RX1 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
when = 1, RX2 FIFO has overflowed and the FIFO pointer
is currently pointing at the last data received before the
overflow occurred.
when = 1, the tx0 FIFO is full and an attempt has been
made to write data to it by the APB or DMA. This bit is
cleared by writing a 0 to it.
Copyright 2007 Cirrus Logic
24 23 22 21
rx1_fifo rx1_fifo rx1_fifo
full _half_ _empty _full
full
8 7 6 5
Tx1_ Tx0_ Rx2_
overflow overflow overflow
2
I S Controller
EP93xx User's Guide
20 19 18 17
tx1_fifo_ tx1_fifo_ tx1_fifo_f rx0_fifo_h
half_ empty ull alf_
empty full
4 3 2 1
Rx1_ Rx0_ Tx2_ Tx1_
overflow overflow underflow underflow
21
16
rx0_fifo_e
mpty
0
Tx0_
underflow
21-29