Cirrus Logic EP93 Series User Manual page 514

SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User's Guide
Register Descriptions
GlConfig
31 30
CKE Clk
Shutdown
13
15 14
Address: 0x8006_0004 - Read/Write
Default: 0x0000_0000
Definition:
Bit Descriptions:
13-18
29 28 27 26
13 12 11 10
RSVD
The Global configuration register contains general control and status bits. The
least-significant two bits, MRS and Initialize, are used in combination as
shown in Table to allow access to otherwise unavailable synchronous
memory commands that are required during memory initialization. The
Synchronous Memory Busy Status bit, SMEMBust, provides the state of the
Synchronous Memory controller, and it can be monitored to determine when a
change of device configuration has taken effect.
RSVD:
CKE:
ClkShutdown:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
ReArb LCR
En
Reserved - Unknown During Read
Synchronous memory Clock Enable - Read/Write
Writing a value to this bit specifies if the enable signal that
is output on the SDCLKEN is asserted, or not:
0 - SDCLKEN is de-asserted to save power only when
there is no current access to any synchronous memory
device
1 - SDCLKEN is continuously asserted (especially useful
when booting from SyncROM or SyncFLASH device
types)
Synchronous memory Clock Shutdown - Read/Write
Writing a value to this bit specifies if the HCLK output on
the SDCLK pin is free-running or gated off:
0 - SDCLK is free-running
1 - SDCLK is gated off only when there is no current
access to any synchronous memory device
21 20 19 18
5 4 3 2
SMEM RSVD
Bust
17 16
1 0
MRS Initialize
DS785UM1