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4 In/4 Out Audio CODEC with PCM and TDM Interfaces
DAC Features
Advanced multibit delta-sigma modulator
24-bit resolution
Differential or single-ended outputs
Dynamic range (A-weighted)
–
-109 dB differential
–
-105 dB single-ended
THD+N
–
-90 dB differential
–
-88 dB single ended
2 Vrms full-scale output into 3-k AC load
Rail-to-rail operation
ADC Features
Advanced multibit delta-sigma modulator
24-bit resolution
Differential inputs
-105 dB dynamic range (A-weighted)
-88 dB THD+N
2 Vrms full-scale input
AIN1 (±)
AIN2 (±)
AIN3 (±)
Multi-bit
AIN4 (±)
ADC
Digital Filters
SDOUT1
VL
1.8 to 5.0 VDC
http://www.cirrus.com
VDREG
2.5 V
Channel Volume ,
Mute, Invert ,
Noise Gate
Serial Audio Interface
Frame Sync
SDOUT2
SDIN2
SDIN1
Clock / LRCK
Copyright Cirrus Logic, Inc. 2014
System Features
TDM, left justified, and I²S serial inputs and outputs
I²C host control port
Supports logic levels between 5 and 1.8 V
Supports sample rates up to 96 kHz
Common Applications
Automotive audio systems
AV, Blu-Ray
Audio interfaces, mixing consoles, and effects
processors
General Description
The CS4244 provides four multibit analog-to-digital and
four multi-bit digital-to-analog - converters and is
compatible with differential inputs and either differential
or single-ended outputs. Digital volume control, noise
gating, and muting is provided for each DAC path. A se-
lectable high-pass filter is provided for the 4 ADC inputs.
The CS4244 supports master and slave modes and
TDM, left-justified, and I²S modes.
This product is available in a 40-pin QFN package in
Automotive (-40°C to +85°C) and Commercial (0°C to
+70°C) temperature grades. The CDB4244 Customer
Demonstration Board is also available for device evalu-
ation and implementation suggestions. See
Information" on page 64
VA
5.0 VDC
LDO
Analog Supply
Master
Volume
Interpolation
Control
Filter
Level Translator
Serial Clock
Master Clock In
In/Out
(All Rights Reserved)
CS4244
®
Disc, and DVD receivers
for complete details.
DAC &
Multi-bit
Analog
Modulators
Filters
Control Port
2
INT
I
C Control
RST
Data
"Ordering
AOUT1 (±)
AOUT2 (±)
AOUT3 (±)
AOUT4 (±)
OCT '14
DS900F2
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Table of Contents
Related Manuals for Cirrus Logic CS4244
Summary of Contents for Cirrus Logic CS4244
- Page 1 DAC path. A se- lectable high-pass filter is provided for the 4 ADC inputs. 24-bit resolution The CS4244 supports master and slave modes and Differential inputs TDM, left-justified, and I²S modes.
-
Page 2: Table Of Contents
CS4244 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ..........................5 1.1 I/O Pin Characteristics ........................6 2. TYPICAL CONNECTION DIAGRAM ....................7 3. CHARACTERISTICS AND SPECIFICATIONS ..................8 RECOMMENDED OPERATING CONDITIONS ..................8 ABSOLUTE MAXIMUM RATINGS ......................8 DC ELECTRICAL CHARACTERISTICS ....................9 TYPICAL CURRENT CONSUMPTION .................... - Page 3 CS4244 LIST OF FIGURES Figure 1.CS4244 Pinout ..........................5 Figure 2.Typical Connection Diagram ......................7 Figure 3.Test Circuit for ADC Performance Testing .................. 13 Figure 4.PSRR Test Configuration ......................13 Figure 5.Equivalent Output Test Load ...................... 16 Figure 6.TDM Serial Audio Interface Timing ..................... 20 Figure 7.PCM Serial Audio Interface Timing .....................
- Page 4 CS4244 LIST OF TABLES Table 1. Speed Modes ..........................26 Table 2. Common Clock Frequencies ....................... 26 Table 3. Master Mode Left Justified and I²S Clock Ratios ................ 27 Table 4. Slave Mode Left Justified and I²S Clock Ratios ................27 Table 5.
-
Page 5: Pin Descriptions
AOUT4- View SDOUT1 VBIAS VREF VDREG Figure 1. CS4244 Pinout Pin Name Pin # Pin Description Serial Control Data (Input/Output) - Bi-directional data I/O for the I²C control port. SDINx Serial Data Input (Input) - Input channels serial audio data. -
Page 6: I/O Pin Characteristics
CS4244 Analog Power (Input) - Positive power for the analog sections. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VREF Analog Power Reference (Input) - Return pin for the VBIAS cap. VBIAS Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs. -
Page 7: Typical Connection Diagram
CS4244 2. TYPICAL CONNECTION DIAGRAM Rp (x4) **** Digital Signal Processor Pull Up or Down Based upon Desired Analog Output Filter * Address AOUT2+ Analog Output Filter * SDIN 1 AOUT2- SDIN 2 AOUT3+ Analog Output Filter * FS/LRCK AOUT3-... -
Page 8: Characteristics And Specifications
CS4244 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 3) Parameters Symbol Units DC Power Supply 3.135 3.465 Analog Core 4.75 5.25 Level Translator 1.71 5.25 Temperature C Ambient Operating Temperature - Power Applied Automotive C... -
Page 9: Dc Electrical Characteristics
CS4244 DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to ground. Parameters Units VDREG (Note 7) Nominal Voltage Output Impedance FILT+ Nominal Voltage Output Impedance k A DC Current Source/Sink Nominal Voltage 0.5•VA Output Impedance k... -
Page 10: Typical Current Consumption
10. PLL is activated by setting the MCLK RATE bit to either 000 (operating in 256x mode) or 001 (operating in 384kHz). 11. Internal to the CS4244, the analog to digital converters are grouped together in stereo pairs. ADC1 and ADC2 are grouped together as are ADC3 and ADC4. The ADC group current draw is the current that is drawn whenever one of these groups become active. -
Page 11: Analog Input Characteristics (Commercial Grade)
CS4244 ANALOG INPUT CHARACTERISTICS (COMMERCIAL GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. Input sine = 25 C; Measurement Bandwidth is 20 Hz to wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T 20 kHz unless otherwise specified;... -
Page 12: Analog Input Characteristics (Automotive Grade)
CS4244 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. Input sine = -40 to +85 C; Measurement Bandwidth is wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T 20 Hz to 20 kHz unless otherwise specified;... -
Page 13: Figure 3.Test Circuit For Adc Performance Testing
CS4244 634 470 pF 90.9 CS4244 AINx + 4.7 uF 100 k Analog Signal + 100 k 100 k 2700 pF 100 k 100 k Analog Signal - 100 k CS4244 AINx - 4.7 uF 90.9 470 pF 634 ... -
Page 14: Adc Digital Filter Characteristics
CS4244 ADC DIGITAL FILTER CHARACTERISTICS Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. Input sine wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified. -
Page 15: Analog Output Characteristics (Commercial Grade)
CS4244 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL GRADE) Test Conditions (unless otherwise specified). Device configured as shown in Section 2. on page VA_SEL = 0 for = 25 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz; Mea- VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T surement Bandwidth is 20 Hz to 20 kHz;... -
Page 16: Analog Output Characteristics (Automotive Grade)
CS4244 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page VA_SEL = 0 for = -40 to +85 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz;... -
Page 17: Combined Dac Interpolation & On-Chip Analog Filter Response
CS4244 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Test Conditions (unless otherwise specified): VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. The filter charac- teristics have been normalized to the sample rate (F... -
Page 18: Digital I/O Characteristics
CS4244 DIGITAL I/O CHARACTERISTICS Parameters Symbol Units High-Level Input Voltage (all input pins except (% of VL) (VL = 1.8 V) High-Level Input Voltage (all input pins except (% of VL) (VL = 2.5 V, 3.3 V, or 5 V) -
Page 19: Switching Characteristics - Serial Audio Interface
CS4244 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. Parameters Symbol Units pin Low Pulse Width (Note 25) MCLK Frequency 7.68 25.6 (Note 26) MCLK Duty Cycle SCLK Duty Cycle... -
Page 20: Figure 6.Tdm Serial Audio Interface Timing
CS4244 FS/LRCK (input) lcks SCLK (input) SDINx MSB-1 (input) SDOUT1 MSB-1 (output) Figure 6. TDM Serial Audio Interface Timing FS/LRCK (input/output) lcks SCLK (input/output) SDINx MSB-1 (input) SDOUTx MSB-1 (output) Figure 7. PCM Serial Audio Interface Timing DS900F2... -
Page 21: Switching Specifications - Control Port
SDA Bus Load Capacitance SDA Pull-Up Resistance Notes: 30. All specifications are valid for the signals at the pins of the CS4244 with the specified load capacitance. 31. 2 ms + (3000/MCLK). See Section 4.2.1. 32. Data must be held for sufficient time to bridge the transition time, t , of SCL. -
Page 22: Applications
4.2.1 Power-up The CS4244 enters a reset state upon the initial application of VA and VL. When these power supplies are initially applied to the device, the audio outputs, AOUTxx, are clamped to VQ which is initially low. Additionally, the interpolation and decimation filters, delta-sigma modulators and control port registers are all reset and the internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and low-pass filters are powered down. -
Page 23: Figure 9.System Level Initialization And Power-Up/Down Sequence
CS4244 4.2.2 Power-down To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn- ing off the power. In order to do this in a controlled manner, it is recommended that all the converters be muted to start the sequence. Next, set PDNx for all converters to 1 to power them down internally. Then, FS/LRCK and SCLK can be removed if desired. -
Page 24: I²C Control Port
However, to avoid potential interference problems, the I²C pins should remain static if no operation is required. The CS4244 acts as an I²C slave device. SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. The AD0 and AD1 pins form the two least significant bits of the chip address and should be connected through a resistor to VL or GND as desired. -
Page 25: Figure 11.Timing, I²C Write
CS4244 The signal timings for a read and write cycle are shown in Figure 11 Figure 12. A Start condition is de- fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. -
Page 26: System Clocking
System Clocking The CS4244 will operate at sampling frequencies from 30 kHz to 100 kHz. This range is divided into two speed modes as shown in... -
Page 27: Figure 13.Master Mode Clocking
CS4244 4.4.2 Master Mode Clock Ratios As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK is equal to F and SCLK is equal to 64x F as shown in Figure 13. TDM format is not supported in Master Mode. -
Page 28: Serial Port Interface
Slave Mode only. 4.5.1 TDM Mode The serial port of the CS4244 supports the TDM interface format with varying bit depths from 16 to 24 as shown in Figure 15. Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. -
Page 29: Figure 16.Serial Data Coding And Extraction Options Within The Tdm Streams
CS4244 DS900F2... -
Page 30: Figure 17.Left Justified Format
Left Justified and I²S Modes The serial port of the CS4244 supports the Left Justified and I²S interface formats with valid bit depths of 16, 18, 20, or 24 bits for the SDOUTx pins and 24 bits for the SDINx pins. All data is valid on the rising edge of SCLK. -
Page 31: Internal Signal Path
ADC Signal Routing In TDM mode, the CS4244 is designed to load the first four slots of the TDM stream on the SDOUT1 pin with the internal ADC data. Additionally, in order to minimize the number of SDOUT lines that must be run... -
Page 32: Figure 20.Conventional Sdout (Left) Vs. Sidechain Sdout (Right) Configuration
Figures 21 and 22. In Left Justified or I²S mode, the CS4244 routes the data on the SDIN1 pin to DAC1 and DAC2 and the data on the SDIN2 pin to DAC3 and DAC4. DS900F2... -
Page 33: Figure 21.Dac1-4 Serial Data Source Selection
CS4244 DS900F2... -
Page 34: Figure 22.Example Serial Data Source Selection
CS4244 DS900F2... -
Page 35: Figure 23.Adc Path
CS4244 4.6.2 ADC Path 2.5 VDC 5.0 VDC 2.5 V Analog Supply AIN1 (±) AIN2 (±) AIN3 (±) Multi-bit AIN4 (±) ADC AOUT1 (±) Master AOUT2 (±) Volume Channel Volume , DAC & AOUT3 (±) Control Interpolation Multi-bit ... -
Page 36: Figure 24.Single-Ended To Differential Active Input Filter
CS4244 634 470 pF ADC1-4 * Place close to AINx pins 91 22 F AINx+ 634 634 2700 pF 100 k 470 pF 100 k 91 100 k AINx- 0.01 F 22 F 100 k... -
Page 37: Figure 26.Dac1-4 Path
4.6.3.1 De-emphasis Filter The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz sample rates. It is not support- ed for 96 kHz or for any settings in Double-speed Mode. The filter response is adjusted to be appropriate... -
Page 38: Figure 27.De-Emphasis Curve
The filter has a single-pole high-pass filter to AC-couple the output signal to the load and a single-pole low-pass filter to attenuate high-frequency energy resulting from the CS4244 DAC’s noise shaping func- tion. -
Page 39: Figure 29.Volume Implementation For The Dac1-4 Path
Noise Gate feature. For any case when the mute engages (volume is less than -90 dB, power down bit is set, mute bit is set, or Noise Gate is engaged), the CS4244 will mute the channel immediately or soft-ramp the volume down at a rate specified by the... -
Page 40: Figure 30.Soft Ramp Behavior
Figure 30 for the soft ramp diagram. On the first volume sample received, the CS4244 only detects the possible beginning of a volume envelope sequence and resets an envelope counter. The volume starts ramping to the new volume setting at a constant rate controlled by the MUTE DELAY[1:0] setting. -
Page 41: Table 6. Soft Ramp Rates
Noise Gate The CS4244 is equipped with a Noise Gate feature that mutes the output if the signal drops below a given bit depth for 8192 samples. While the enabling or disabling of the Noise Gate feature is done for the entire DAC1-4 output path, each of the channels within the path have separate monitoring circuitry that will trig- ger the Noise Gate function independently of the other channels. -
Page 42: Reset Line
Reset Line The reset line of the CS4244 is used to place the device into a reset condition. In this condition, all of the values of the CS4244 control port are set to their default values. This mode of operation is the lowest power mode of operation for the CS4244 and should be used whenever the device is not operating in order to save power. - Page 43 If the CS4244’s interrupt line is to be connected onto a single bus with other devices, it is advisable to use it in the open drain mode of operation. If no other devices are connected to the interrupt line, it may be used in the CMOS mode of operation.
-
Page 44: Figure 31.Interrupt Behavior And Example Interrupt Service Routine
CS4244 USER: Mask bit(s) set to 0 Unmasked error occurs Status Register bit changes to ‘1’ and INT pin set to active level USER: Read Status Registers (see status bit(s) = ‘1’) Mask bit(s) of corresponding status bit(s) set to ‘1’... -
Page 45: Register Quick Reference
CS4244 5. REGISTER QUICK REFERENCE Default values are shown below the bit names Function (Read Only Bits are shown in Italics) DEV. ID A[3:0] DEV. ID B[3:0] Device ID A & B p 48 DEV. ID C[3:0] DEV. ID D[3:0] Device ID C &... - Page 46 CS4244 Function (Read Only Bits are shown in Italics) MUTE DELAY[1:0] MIN DELAY[2:0] MAX DELAY[2:0] Volume Mode p 55 MASTER VOLUME[7:0] Master Volume p 56 DAC1 VOLUME[7:0] DAC1 Volume p 56 DAC2 VOLUME[7:0] DAC2 Volume p 56 DAC3 VOLUME[7:0] DAC3...
-
Page 47: Register Descriptions
DEV. ID C[3:0] DEV. ID D[3:0] DEV. ID E[3:0] DEV. ID F[3:0] 6.1.1 Device I.D. (Read Only) Device I.D. code for the CS4244. Example:. DEV. ID A[3:0] DEV. ID B[3:0] DEV. ID C[3:0] DEV. ID D[3:0] DEV. ID E[3:0] DEV. ID F[3:0]... -
Page 48: Clock & Sp Select (Address 06H)
Auto Detect (Slave Mode only) 6.3.3 Master Clock Rate Sets the rate at which the master clock is entering the CS4244. Settings are given in “x” multiplied by the incoming sample rate, as MCLK must scale directly with incoming sample rate. MCLK RATE... -
Page 49: Sample Width Select (Address 07H)
Bits wider than the Output Sample Width setting are cleared within the SDOUTx data stream. 6.4.2 Input Sample Width These bits set the width of the samples coming into the CS4244 through the SDINx TDM streams. INPUT SW Sample Width is:... -
Page 50: Serial Port Data Select (Address 09H)
Setting this bit places the CS4244 in master mode, clearing it places it in slave mode. MASTER/SLAVE CS4244 is in: Slave Mode Master Mode Note: I²S and Left Justified are the only serial port formats available if the CS4244 is in Master Mode. Serial Port Data Select (Address 09h) Reserved Reserved DAC1-4 SOURCE[2:0] Reserved[2:0] 6.6.1... -
Page 51: Adc Control 1 (Address 0Fh)
CS4244 ADC Control 1 (Address 0Fh) Reserved Reserved VA_SEL ENABLE HPF INV. ADC4 INV. ADC3 INV. ADC2 INV. ADC1 6.7.1 VA Select Scales internal operational voltages appropriately for VA level. Configuring this bit appropriately for the VA voltage level used in the application is imperative to ensure proper operation of the device. -
Page 52: Dac Control 1 (Address 12H)
Enables or disables de-emphasis for the DAC1-4 path. See Section 4.6.3.1 for details. The CS4244 in- cludes on-chip digital de-emphasis for 32, 44.1, and 48 kHz base rates. It is not supported for 96 kHz or for any settings in Double-speed Mode. -
Page 53: Dac Control 3 (Address 14H)
CS4244 6.11 DAC Control 3 (Address 14h) Reserved DAC1-4 ATT Reserved Reserved MUTE DAC4 MUTE DAC3 MUTE DAC2 MUTE DAC1 6.11.1 DAC1-4 Attenuation Sets the mode of attenuation used for the DAC1-4 path. DAC1-4 ATT Attenuation events happen: On a soft ramp... -
Page 54: Volume Mode (Address 16H)
CS4244 6.13 Volume Mode (Address 16h) MUTE DELAY[1:0] MIN DELAY[2:0] MAX DELAY[2:0] 6.13.1 Mute Delay Sets the delay between the volume steps during muting and unmuting of a signal when attenuation mode 6.02 is set to soft ramp. Each step of the ramp is equal to dB ~= 0.094 dB. -
Page 55: Master And Dac1-4 Volume Control (Address 17H, 18H, 19H, 1Ah, & 1Bh)
In the nondefault configuration, mask bits are not set automatically. INT MODE Upon the reading of an error out of the interrupt notification bits, the CS4244 will: Automatically set the corresponding mask bit. Not set the corresponding mask bit. -
Page 56: Interrupt Mask 1 (Address 1Fh)
CS4244 6.16 Interrupt Mask 1 (Address 1Fh) MASK MASK MASK MASK MASK MASK MASK CLK ERR Reserved TST MODE ERR SP ERR ADC4 OVFL ADC3 OVFL ADC2 OVFL ADC1 OVFL 6.16.1 Test Mode Error Interrupt Mask Controls whether a Test Mode Error event flags the interrupt pin. A test mode error occurs when an inad- vertent I²C write places the device in test mode. -
Page 57: Interrupt Mask 2 (Address 20H)
CS4244 6.17 Interrupt Mask 2 (Address 20h) MASK DAC4 MASK DAC3 MASK DAC2 MASK DAC1 Reserved Reserved Reserved Reserved CLIP CLIP CLIP CLIP 6.17.1 DACx Clip Interrupt Mask Allows or prevents a DACx Clip event from flagging the interrupt pin. -
Page 58: Interrupt Notification 2 (Address 22H) (Read Only)
CS4244 6.19 Interrupt Notification 2 (Address 22h) (Read Only) Reserved Reserved Reserved Reserved DAC4 CLIP DAC3 CLIP DAC2 CLIP DAC1 CLIP 6.19.1 DACx Clip A DACx Clip has occurred since the last clearing of the Interrupt Notification register. DACx CLIP... -
Page 59: Adc Filter Plots
CS4244 7. ADC FILTER PLOTS Stopband Rejection a s t o −10 −10 −20 −20 −30 −30 −40 −40 −50 −50 −60 −60 −70 −70 −80 −80 −90 −90 −100 −100 0.42 0.44 0.46 0.48 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 32. -
Page 60: Dac Filter Plots
CS4244 8. DAC FILTER PLOTS Figure 38. SSM DAC Stopband Rejection Figure 39. SSM DAC Transition Band Figure 40. SSM DAC Transition Band (Detail) Figure 41. SSM DAC Passband Ripple DS900F2... -
Page 61: Figure 42.Dsm Dac Stopband Rejection
CS4244 Figure 42. DSM DAC Stopband Rejection Figure 43. DSM DAC Transition Band Figure 44. DSM DAC Transition Band (Detail) Figure 45. DSM DAC Passband Ripple DS900F2... -
Page 62: Package Dimensions
CS4244 9. PACKAGE DIMENSIONS 40L QFN (6 6 MM BODY) PACKAGE DRAWING 2.00 REF PIN #1 CORNER PIN #1 IDENTIFIER 0.500.10 LASER MARKING Figure 46. Package Drawing INCHES MILLIMETERS NOTE 0.0315 0.0354 0.0354 0.85 0.0014 0.002 0.035 0.05 0.0078 0.0098 0.011 0.25 0.2362 BSC... -
Page 63: 10.Ordering Information
TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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