Cirrus Logic EP93 Series User Manual page 254

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
7
CursorBlinkRateCtrl
31 30
15 14
Address: 0x8003_0224
Default: 0x0000_0000
Definition: Blink Rate Control register
Bit Descriptions:
7-72
29 28 27 26
13 12 11 10
RSVD
RSVD:
EN:
Copyright 2007 Cirrus Logic
When Dual Scan mode is enabled by writing DSCAN = '1'
in the PixelMode register, the Y Location value written to
this field specifies the starting vertical Y location (in the
lower half of the display) of the cursor image. The value is
compared to the vertical line counter and it should be
specified to be between the active start and active stop
vertical line values.
The cursor hardware will clip the cursor at the bottom of
the display. To prevent cursor distortion, a new Y Location
value will not be used until the next frame.
25 24 23 22
RSVD
9 8 7 6
EN
Reserved - Unknown during read
Enable - Read/Write
Writing a '1' to this bit enables hardware cursor blinking
and enables the blink rate counter. Writing a '0' to this bit
disables hardware cursor blinking and disables the blink
rate counter:
0 - Hardware cursor blinking not enabled
1 - Hardware cursor blinking enabled
When EN = '1' and the 2-bit cursor pixel fetched from
SDRAM is '10', CursorColor2,
the blink toggle and CursorColor1,
of the blink toggle.
When EN = '1' and the 2-bit cursor pixel fetched from
SDRAM is '11', CursorBlinkColor1,
of the blink toggle and
part of the blink toggle.
21 20 19 18
5 4 3 2
RATE
is used for the 'on' part of
is used for the 'off' part
is used for the 'on' part
CursorColor1, is used for the 'off'
17 16
1 0
DS785UM1