Cirrus Logic EP93 Series User Manual page 96

MaverickCrunch Co-Processor
EP93xx User's Guide
31:28
3
cond 1 1 1 0
Description:
Mnemonic:
Bit Definitions:
31:28
cond 1 1 1 0
Description:
Mnemonic:
Bit Definitions:
31:28
cond 1 1 1 0
Description:
Mnemonic:
Bit Definitions:
3-26
Move Lower Half 64-bit Integer from ARM to MaverickCrunch
27:24 23:22 21
0 0 0
Moves the lower half of a 64-bit integer from an ARM register into the lower
half of a MaverickCrunch register and sign extend it.
CFMV64LR<cond> CRn, Rd
CRn:
Rd:
Move Lower Half 64-bit Integer from MaverickCrunch to ARM
27:24 23:22 21
0 0 0
Moves the lower half of a 64-bit integer stored in a MaverickCrunch register
into an ARM register.
CFMVR64L<cond> Rd, CRn
Rd:
CRn:
Move Upper Half 64-bit Integer from ARM to MaverickCrunch
27:24 23:22 21
0 0 0
Moves the upper half of a 64-bit integer from an ARM register into the upper
half of a MaverickCrunch register.
CFMV64HR<cond> CRn, Rd
CRn:
Rd:
20 19:16 15:12
0 CRn Rd
Destination register
Source ARM register
20 19:16 15:12
1 CRn Rd
Destination ARM register
Source register
20 19:16 15:12
0 CRn Rd
Destination register
Source ARM register
Copyright 2007 Cirrus Logic
11:8 7:5 4
0 1 0 1 0 0 0 1
11:8 7:5 4
0 1 0 1 0 0 0 1
11:8 7:5 4
0 1 0 1 0 0 1 1
DS785UM1
3:0
CRm
3:0
CRm
3:0
CRm