Cirrus Logic EP93 Series User Manual page 144

System Controller
EP93xx User's Guide
STFClr
5
31 30
15 14
Address:
Definition:
Bit Descriptions:
ClkSet1
31 30
RSVD
15 14
PLL1 X1FBD1
Address:
Definition:
Note: When a write is performed to the ClkSet1 location, it must be immediately followed by 5
Bit Descriptions:
Note: The value in the register is the actual coefficient minus one.
5-18
29 28 27 26
13 12 11 10
0x8093_001C - Write
Writing to the STFClr location will clear the CLDFLG, WDTFLG and RSTFLG
in the register, "PwrSts" on page
the clearing.
RSVD:
29 28 27 26
FCLK DIV
13 12 11 10
0x8093_0020 - Read/Write
The ClkSet1 system control register is one of two register that control clock
speeds.
NOP instructions. This is needed to flush the instruction pipeline in the ARM920T core.
Writing to this register will cause the the device to enter Standby for between 8 ms to
16 ms. Reading from this register will not cause an entry into Standby mode.
RSVD:
PLL1_X2IPD:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
RSVD
5-14. Any data written to the register triggers
There are no readable bits in this register.
25 24 23 22
SMC ROM nBYP1
9 8 7 6
PLL1 X2FBD2
Reserved. Unknown During Read.
These 5 register bits set the input divider for PLL1
operation. On power-on-reset the value is set to 00111b (7
decimal).
21 20 19 18
5 4 3 2
21 20 19 18
HCLK DIV PCLK DIV
5 4 3 2
PLL1 X2IPD
17 16
1 0
17 16
PLL1_PS
1 0
DS785UM1