Cirrus Logic EP93 Series User Manual page 543

Definition:
UART Line Control Register Middle.
Bit Descriptions:
RSVD:
BR:
UART1LinCtrlLow
31 30 29 28
15 14 13 12
Address:
0x808C_0010 - Read/Write
Default:
0x0000_0000
Definition:
UART Line Control Register Low.
Bit Descriptions:
RSVD:
BR:
DS785UM1
Reserved. Unknown During Read.
Baud Rate Divisor bits [15:8]. Most significant byte of baud
rate divisor. These bits are cleared to 0 on reset.
27 26 25
11 10 9
RSVD
Reserved. Unknown During Read.
Baud Rate Divisor bits [7:0]. Least significant byte of baud
rate divisor. These bits are cleared to 0 on reset. The baud
rate divisor is calculated as follows:
Baud rate divisor
BAUDDIV = (F
where F
baud rate divisor of zero is not allowed and will result in no
data transfer.
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
24 23 22 21
RSVD
8 7 6 5
/ 16 * Baud rate)) – 1
UARTCLK
is the UART reference clock frequency. A
UARTCLK
EP93xx User's Guide
20 19 18 17
4 3 2 1
BR
14
16
0
14-21